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g m s81508a g m s81516a use r s m an u al re v isio n history re v 2.2 (dec. 1 9 9 8) add t he package di m en s i o n f o r 64lq f p o n page 3- 1 , 4-1. re v 2.1 (no v . 1998) o p e r a t i n g t e m p e r a tu r e, - 1 0 ~ 7 5 c i s e xt e n d e d to - 20~ 8 5 c. add t h e u n us e d p o r t gui d a n c e o n p a g e 5 5 . c o r r e c t e rra t a f o r o p c o d e o f eo r [dp+x] , eo r [dp ] +y , eo r {x} i n i n s t ru c ti o n s e t. a d d t h e o t p d e v i ce p r o g r a m m i n g g u i d a n ce , r eco m m e n d u s i n g i n t el li g e n t mo d e . ad d t h e c hapt e r f o r otp p r o gra m m i ng m a nu a l as a n app e n di x . re v 2.0 ( s ep. 1 9 97)
- contents - 1. overview.................................................................................................................... .......................1 1.1. features .................................................................................................................. ........................1 1.2. block diagram............................................................................................................. .................2 1.3. pin assignment............................................................................................................ ..................3 1.4. package dimension .....................................................................................................................4 1.5. pin description........................................................................................................... ...................5 2. functions ............................................................................................................................... ...........7 2.1. registers ................................................................................................................. ........................7 2.1.1. a - register............................................................................................................ ........................8 2.1.2. x- register............................................................................................................. ........................8 2.1.3. y- register ............................................................................................................. ........................8 2.1.4. stack pointer ........................................................................................................... ......................8 2.1.5. program counter......................................................................................................... ................10 2.1.6. program status word..................................................................................................... ..............10 2.2. memory space.............................................................................................................. ................12 2.2.1. ram area ................................................................................................................ ....................12 2.2.2. peripheral register area ................................................................................................ ..............12 2.2.3. program rom area ........................................................................................................ .............12 2.2.4. peripheral register list ................................................................................................ ...............14 2.3. clock generation circuit .................................................................................................. ...16 2.3.1. oscillation circuit ..................................................................................................... ..................16 2.3.2. prescaler ............................................................................................................... ......................17 2.4. basic interval timer...................................................................................................... ..........18 2.4.1. control of basic interval timer......................................................................................... ...........18 2.5. watch dog timer ........................................................................................................................19 2.5.1. control of watch dog timer .............................................................................................. ..........19 2.5.2. the output of wdt signal................................................................................................ .............20 2.6. timer..................................................................................................................... ...........................21 2.6.1. control of timer ........................................................................................................ ..................23 2.6.2. interval timer.......................................................................................................... ....................24 2.6.3. event counter........................................................................................................... ...................24 2.6.4. pulse output ............................................................................................................ ....................24 2.6.5. input capture........................................................................................................... ....................24 2.7. external interrupt........................................................................................................ ..........26 2.8. a/d converter .............................................................................................................................27 2.8.1. control of a/d converter................................................................................................ .............27 2.9. serial i/o ................................................................................................................ ........................29 2.9.1. data transmission/receiving timing ...................................................................................... .....31 2.9.2. the serial i/o operation by srdy pin .................................................................................... ........31 2.9.3. the method of serial i/o ................................................................................................ ..............32 2.9.4. the method to test correct transmission with s/w ......................................................................32 2.10. pwm ...................................................................................................................... ..........................33 2.10.1. controls of pwm ........................................................................................................ ...............33 2.11. buzzer driver............................................................................................................ ................35 2.11.1. buzzer driver operation ................................................................................................ ............36 2.12. interrupts............................................................................................................... ....................37 2.12.1. interrupt circuit configuration and kinds.............................................................................. ....37 2.12.2. interrupt control...................................................................................................... ..................38 2.12.3. interrupt priority ..................................................................................................... ..................39
2.12.4. interrupt sequence..................................................................................................... ................ 40 2.12.5. software interrupt ..................................................................................................... ................ 41 2.12.6. multiple interrupt ..................................................................................................... ................. 42 2.13. standby function ................................................................................................................... 44 2.13.1. stop mode.............................................................................................................. ................. 45 2.13.2. stop mode release ...................................................................................................... ............ 45 2.14. reset function ........................................................................................................... .............. 47 3. i/o ports................................................................................................................... ........................ 48 3.1. r0 port................................................................................................................... ......................... 48 3.2. r1 port................................................................................................................... ......................... 49 3.3. r2 port................................................................................................................... ......................... 50 3.4. r3 port................................................................................................................... ......................... 51 3.5. r4 port................................................................................................................... ......................... 52 3.6. r5 port................................................................................................................... ......................... 53 3.7. r6 port ........................................................................................................................... ................. 54 3.8. terminal types............................................................................................................ ............... 56 4. electrical characteristics ............................................................................................... 60 4.1. aboulute maximum ratings................................................................................................. 6 0 4.2. recommended operating conditions ............................................................................... 60 4.3. a/d converter characteristics ......................................................................................... 60 4.4. dc characteristics ........................................................................................................ .......... 61 4.5. ac characteristics ........................................................................................................ .......... 62 4.5.1. input conditions........................................................................................................ .................. 62 4.5.2. serial transfer ......................................................................................................... ................... 63 4.5.3. microprocessor mode i/o timing .......................................................................................... ...... 64 4.5.4. bus holding timing...................................................................................................... ............... 65 5. instruction set ........................................................................................................................... 66
GMS81508/16 1 1. overview GMS81508/16 is a single chip microcomputer designed cmos technology. the use of cmos process enables extremely low power consumption. this device using the g8mc core includes several peripheral functions such as timer, a/d converter, programmable buzzer driver, serial i/o, pulse width modulation function, etc. rom,ram,i/o are placed on the same memory map in addition to simple instruction set. 1.1. features GMS81508 gms81516 rom(bytes) 8k 16k ram(bytes) 448 bytes(includes stack area) execution time 0.5us (@xin=8mhz) basic interval timer 8bit 5 1ch. watch dog timer 6bit 5 1ch. timer 8bit 5 4ch.(or 16bit 5 2ch.) adc 8bit 5 8ch. pwm 8bit 5 2ch. serial i/o 8bit 5 1ch. external interrupt 4ch. buzzer driver programmable buzzer driving port i/o port 4 - input only 52 - input/output power save mode stop mode operating voltage 4.5 ~ 5.5v ( @ xin=8mhz ) operating frequency 1 ~ 8mhz package 64sdip, 64qfp otp gms81516t application home appliances, led applications
h y undai microelectronics 2 1.2. bloc k di a g r a m a / d c onverter pwm b uzzer w . d.t s. i .c timer i n te r r u p t c l o ck gen. / system c ontrol g 8 mc c o r e r a m ( 4 4 8 b y t e) r o m (8/1 6 k b y t e) prescaler / b . i . t r6 p o rt r5 p o rt r4 p o rt r3 p o rt r2 p o rt r1 p o rt r0 p o rt a v r e f a v s s r60 ~ r67 ( a n 0 ~ an 7 ) r57 / p w m 1 r55 / b u z r56 / p w m 0 r54 / w d to r53 / s r dy r52 / s c l k r51 / s o u t r50 / s i n r47 / t 3 o r46 / t 1 o r45 / e c2 r44 / e c0 r43 / i n t 3 r42 / i n t 2 r41 / i n t 1 r40 / i n t 0 mp r e s e t x i n x o u t v d d v s s r60 : r63 r64 : r67 r50 : r57 r40 : r47 r30 : r37 r20 : r27 r10 : r17 r00 : r07
GMS81508/16 3 1.3. pin assignment g m s 8 1 5 0 8 / 1 6 r30/ rd r31/ wt r32/ r/w r33/ c r34/ sync r35/ brk r36/ brq r37/ halt r00/ d0 r01/ d1 r02/ d2 r03/ d3 r04/ d4 r05/ d5 r06/ d6 r07/ d7 r10/ a0 r11/ a1 r12/ a2 r13/ a3 r14/ a4 r15/ a5 r16/ a6 r17/ a7 r20/ a8 r21/ a9 r22/ a10 r23/ a11 r24/ a12 r25/ a13 r26/ a14 r27/ a15 vdd mp avss avref r67/an7 r66/an6 r65/an5 r64/an4 r63/an3 r62/an2 r61/an1 r60/an0 r57/pwm1 r56/pwm0 r55/buz r54/wdto r53/srdy r52/sclk r51/sout r50/sin r47/t3o r46/t1o r45/ec2 r44/ec0 r43/int3 r42/int2 r41/int1 r40/int0 reset xin xout vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 mp mode 64 sdip GMS81508/16 r65/an5 r64/an4 r63/an3 r62/an2 r61/an1 r60/an0 r57/pwm1 r56/pwm0 r55/buz r54/wdto r53/srdy r52/sclk r51/sout r50/sin r47/t3o r46/t1o r45/ec2 r44/ec0 r43/int3 21 3 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 20 49 51 50 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 62 61 60 59 58 57 56 55 54 53 52 64 r37/halt r00/d0 r01/d1 r02/d2 r03/d3 r04/d4 r05/d5 r06/d6 r07/d7 r10/a0 r11/a1 r12/a2 r13/a3 r14/a4 r15/a5 r16/a6 r17/a7 r20/a8 r21/a9 r22/a10 r23/a11 r24/a12 r25/a13 r26/a14 r17/a15 vss xout xin reset r40/int0 r41/int1 r42/int2 r36 brq r35 bak r34 sync r33 c r32 r/w r31 wt r30 rd vdd mp avss avref r67/an7 r66/an6 64 qfp
hyundai microelectronics r20 r21 r22 r23 r24 r25 r26 r27 vss xout x i n reset r40/int0 r41/int1 r42/int2 r43/int3 r0 0 r0 1 r0 2 r0 3 r0 4 r0 5 r0 6 r0 7 r1 0 r1 1 r1 2 r1 3 r1 4 r1 5 r1 6 r1 7 r6 3/ an3 r6 2/ an2 r6 1/ an1 r6 0/ an0 r 57/ p w m1 r 56/ p w m0 r55 / buz r54 / w d t o r53/srdy r52/ s c l k r5 1 /so ut r5 0 /si n r4 7/ t 3 o r4 6/ t 1 o r4 5/ ec2 r4 4/ ec0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r 3 7 r 3 6 r 3 5 r 3 4 r 3 3 r 3 2 r 3 1 r 3 0 vdd mp a vss avr e f r67/an7 r66/an6 r65/an5 r64/an4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GMS81508 / 16 64lqfp 3-1
hyundai microelectronics 4 1.4 package dimension unit: inch 2 . 2 8 0 2 . 2 6 0 0 .2 0 5 max. 0.022 0.016 0.0 5 0 0.030 0.070 bsc 0. 1 4 0 0. 1 2 0 m i n. 0. 015 0.680 0.660 0.750 bsc 0-15 0.012 0.008 64sdip 20.10 19.90 24.15 23.65 18 . 1 5 17 . 6 5 14 . 1 0 13 . 9 0 3.18 max. 0.50 0.35 1 .00 bsc s e e d e ta i l " a " 1.03 0.73 0-7 0. 36 0. 10 0. 23 0. 13 1.95 ref detail "a" unit: mm 64 q fp
hyundai microelectronics 1.60 m a x. see detail " a " 0.75 0 . 4 5 0-7 0. 1 5 0. 0 5 1 . 0 0 ref detail "a" unit: mm 10.00 bsc 12.00 bsc 1 2 . 0 0 bsc 1 0 . 0 0 bsc 0. 3 8 0. 2 2 0.50 bsc 1. 45 1. 35 64lq f p 4-1
GMS81508/16 5 1.5. pin description classification no. symbol i/o descriptions power 1 vdd i power supply input pin(4.5~5.5v) 32 vss i ground(0v) 2mp i controls microprocess mode of the chip at "h" input : single chip mode at "l" input : microprocess mode system control or 29 reset i in the state of "l" level, system enter to the reset state. clock 30 xin i this chip has an internal clock generating circuit. to control generating frequency, an external ceramic or a quartz crystal oscillator is connected between xin and xout pins. 31 xout i if external clock is used, the clock source should be connected to the xin pin and the xout pin should be left open. 24 ec0 i event counter source clock input pin timer 23 ec2 i 22 t1o o timer counter overflow output pin 21 t3o o 28 int0 i ext. interrupt 27 int1 i external interrupt request signal input pin 26 int2 i 25 int3 i 4 avref i reference voltage input pin for a/d converter 3 avss i ground level input pin for a/d converter 12 an0 i 11 an1 i a/d converter 10 an2 i 9 an3 i analog voltage input pin for a/d converter 8an4 i 7an5 i 6an6 i 5an7 i 17 srdy i/o receive enable output pin serial i/o 18 sclk i/o serial clock output pin 19 sout o serial data output pin 20 sin i serial data input pin p.w.m 14 pwm0 o pwm pulse output pin 13 pwm1 o buzzer 15 buz o buzzer driving frequency output pin w.d.t 16 wdto o watch dog timer overflow output pin
hyundai microelectronics 6 c l ass i f i cati o n n o . sym b ol i / o descr i p t i on 49 : 56 r00 : r07 i/o r0 port ( can be de t e r m i ned i / o by r0dd ) i n m p m ode, t h i s port f unct i on s a s 8-b i t da t a bu s f o r t he cpu. (d0 ~ d7) 41 : 48 r10 : r17 i/o r1 port ( can be de t e r m i ned i / o by r1dd ) i n m p m ode, t h i s f un c t i on s a s 8-b i t l o w e r address ou t put p i n s . (a 0 ~ a7) 33 : 40 r20 : r27 i/o r2 port ( can be de t e r m i ned i / o by r2dd ) i n m p m ode, t h i s f un c t i on s a s 8-b i t h i gher addre s s ou t put p i n s . (a8~a15) i/ o p o rt 5 7 : 64 r30 : r37 i/o r3 port ( can be de t e r m i ned i / o by r3dd ) i n m p m ode, t h i s port f unct i on s a s 8-b i t control bus f o r t he cp u . 28 : 21 r40 : r47 i/o r4 port ( can be de t e r m i ned i / o by r4dd ) 20 : 13 r50 : r57 i/o r5 port ( can be de t e r m i ned i / o by r5dd ) 12 : 9 r60 : r63 i r6 port i nput o n l y 8 : 5 r64 : r65 i/o r 6 p o rt ( can be de t e r m i ned i / o by r6dd )
GMS81508/16 7 2. functions 2.1. registers 6 registers are built-in the cpu of g8mc. accumulator(a), index register x, y, stack pointer (sp) and program status word(psw) consists of 8-bit registers. program counter(pc) consists of 16- bit registers. the contents of these registers are undefined after reset. p rogram c ounter 15 8 pch 7 0 pcl a - register 7 0 a 15 8 y ( ya 16bit accumulator ) 7 0 a x - register 7 0 x y - register 7 0 y p rogram s tatus w ord 7 0 psw s tack p ointer 7 0 sp c arry flag z c h i g b n v z ero flag i nterrupt e nable flag h alf carry flag b reak flag g ( direct page ) flag o verflow flag n egative flag
hyundai microelectronics 8 2.1.1. a - reg i s ter t he acc u m u l a t o r i s t he 8- b i t gener a l purpo s e reg i s t er. t h i s i s u s ed reg i s t er f o r da t a opera t i on, da t a t ran s f e r, t e m porar y s a v e s and cond i t i onal j ud g m en t . acc u m u l a t o r can be u s ed a s a 16-b i t re g i s t er w i t h y reg i s t er and ha s a l o w e r 8-b i t da t a. i n ca s e of m u l t i pl i c a t i o n i n s t ruct i on(mul), i t w ork s a s a m u l t i pl i er. a f t er e x ec u t i on o f mul i n s t ruc t i o n , a c c u m u l a t o r ha s l o w e r 8-b i t d a t a o f t he re s u l t s (16-b i t ) . i n ca s e of d i v i s i o n i n s t ruct i on(d i v ) , i t ha s t he l o w er 8-b i t o f d i v idend (16-bi t ) 2.1.2. x- reg i s t er i n i nd e x addres s i ng m ode, t h i s reg i s t er i s e x ec u t ed a s a 8-b i t i ndex reg i s t er w i t h i n d i rect page(ram area). a l s o , i n i n d i rect addre s s i ng m ode, i t i s de s t i na t i on addre s s reg i s t er. t h i s reg i s t er ca n be u s ed a s a i n cre m e n t , decr e m e n t , c o m par i s on, and da t a t ran s f e r f unct i on. i n ca s e of d i v i s i o n i n s t ruct i on(d i v ) , i t w ork s a s a di v i s or. 2.1.3. y- reg i s t er i n i nd e x addres s i ng m ode, t h i s reg i s t er i s e x ec u t ed a s a i nd e x re g i s t er. i n ca s e of 16-bit operat i o n i n s t ruc t i on, t h i s reg i s t er ha s upper 8-b i t o f y a (16-bit a c c u m u l a t o r ). i n ca s e of m u l t i pl i c a t i o n i n s t ruct i on(mul), t h i s reg i s t er i s e x ec u t ed a s a m ul t i p l i cand reg i s t er. a f t er m u l t i p l icat i on opera t i on, i t ha s t he upper 8- b i t o f t he re s u l t . i n ca s e of d i v i s i o n i n s t ruct i on, i t i s e x ec u t ed a s a di v idend(upper 8-b i t ) . a f t e r di v i s i on operat i on, i t ha s quo t i en t . t h i s reg i s t er ca n be u s ed a s a l oop coun t er o f con d i t i onal branch c o m m and. (e . g. dbne y, r e l ) 2.1.4 . stack po i nt e r t he s t ack po i n t er(sp ) i s an 8- b i t reg i s t er u s ed dur i ng s ubrou t i ne call i ng an d i n t e rrup t s . w he n branch i ng out f r o m an on-go i ng rout i n e t o s ubrou t i ne or i n t e rrupt rout i ne, i t i s neces s a ry t o re m e m be r t he r e t urn addre s s . nor m al l y, i n t ernal ra m i s u s ed f o r s t or i n g t he re t urn addre s s and t h i s area i s c a l l ed s t ack area. s p i s po i n t e r t o s ho w w here t he s t ack da t a are s t ored w i t h i n t h e s t ack area. t he s t ack are a i s l oca t e d i n 1 - page o f i n t ern a l ra m . s p m u s t b e i n i t i al i zed b y s / w becau s e t he con t en t s of sp i s und e f i ned a f t er r e set. e x ) ldx #0 f eh ; 0 f eh - > x reg i s t er t x sp ; x -> s p ca u t i o n ) you ca n ' t u se !01f f h as stack. i f y o u u se th i s area, ma l - f u n c t i on w o u ld b e o cc u rre d .
GMS81508/16 9 the bellows shows data store and restore sequence to/from stack area. interrupt reti subroutine call ret push a ( x, y, psw ) pop a ( x, y, psw ) m (sp) ( pch ) sp sp 1 m (sp) ( pcl ) sp sp 1 m (sp) a m (sp) ( pch ) sp sp 1 m (sp) ( pcl ) sp sp 1 m (sp) ( psw ) sp sp 1 sp sp 1 sp sp 1 ( pcl ) m (sp) sp sp 1 ( pch) m (sp) sp sp 1 a m (sp) ( psw ) m (sp) sp sp 1 ( pcl ) m (sp) sp sp 1 ( pch) m (sp) sp sp 1 15 8 stack address ( 0100 h 01ff h ) 01 h 7 0 sp hardware fixed
hyundai microelectronics 10 2.1.5. p rogra m counter t he progr a m coun t er(pc ) i s a 16-b i t coun t er w h i ch con s i s t s of 8-bit re g i s t er pch and pcl. t he addres s i ng s pace i s 64k by t e s . t h i s coun t er i ndica t e s t he addre ss of t he n e x t i n s t ruc t i o n t o be e x ecu t e d . i n re s e t s t a t e, t h e program coun t er ( pc) ha s re s e t rou t i ne addre ss i n addres s ff f f h and ff f eh . 2.1.6. p rogra m s tatu s w ord p s w i s an 8- b i t re g i s t er w h i c h i s co m po s ed o f f l ag s t o m a i n t a i n t he condi t i on o f t h e proce s s o r im m e d i a t e l y a f t er an operat i on. a f t er r es e t , t he con t en t s o f p s w i s s et t o " 00h " . p s w carry f l a g ( c ) a f t er a n opera t i on, it i s s et t o " 1 " w hen t here i s a carr y f r o m bi t 7 o f alu or n o t a borro w . se t c , clr c i n s t ruct i on s a l l o w d i re c t acce ss f o r s e tt i ng and re s e t t i ng. i t can be u s ed a s a 1-b i t acc u m u l a t o r . i t i s a branch condit i o n f l ag o f bcs, bc c i n s t ruct i on s . zero f l ag ( z ) a f t e r a n opera t i o n i n c l ud i ng 16- b i t opera t i on, it i s s e t t o " 1 " w hen t he re s u l t i s 0. i t i s a branch condit i o n f l ag o f b e q , bne. inter r upt e na b l e f l a g ( i ) t h i s f l a g i s u s ed t o enab l e / d i s ab l e a l l i n t e rrup t s except i n t e rrupt cau s ed by brk i n s t ruct i on. w he n t h i s f l a g i s " 1 " , i t mean s i n t e rrupt enab l e condi t i o n . w hen an i n t e rrupt i s accep t , t h i s f l ag i s au t o m at i c a l l y s et t o " 0 " t hereby pr e v ent i ng o t her i n t e r rup t s . a l s o it i s s et t o " 1 " by r e t i i n s t ruct i on. t h i s f l a g i s s et and c l eared by e i , di i n s t ruct i on s . ha l f c a rry f l ag ( h ) a f t er a n opera t i on, it i s s et w hen t here i s a carry f r o m b i t 3 o f alu or i s not a borro w f r o m b i t 4 o f alu. i t ca n not be s et by an y i n s t ruct i on. it i s c l eared by clrv i n s t ruct i on l i k e v f l a g . 7 n 6 v 5 g 4 b 3 h 2 i 1 z 0 c
GMS81508/16 11 break flag ( b ) this flag is set by brk (s/w interrupt) instruction to distinguish brk and tcall instruction having the same vector address. direct page flag ( g ) this flag assign direct page (0-page, 1-page) for direct addressing mode. when g-flag is "0", the direct addressing space is in 0-page(0000h~00ffh). when g-flag is "1", the direct addressing space is in 1-page(0100h~01ffh). it is set and cleared by setg, clrg instruction overflow flag ( v ) this flag functions when one word is added or subtracted in binary with the sign. when results exceeds +127 or -128, this flag is set. when bit instruction is executed, the bit6 of memory is input into v-flag. this flag is cleared by clrv instruction, but set instruction is not exist. it is a branch condition flag of bvs, bvc. negative flag ( n ) n-flag is set when the result of a data transfer or operation is negative (bit7 is 1). it means the bit-7 of memory is sign bit. thereby data is valid in the range of -128 ~ +127. when bit instruction is executed, the bit7 of memory is input into n-flag. set or clear instruction is not exist. it is a branch condition flag of bpl, bmi instruction.
hyundai microelectronics 12 2.2. m e m ory s p a ce all r a m , r o m ,i / o , pe r i pheral re g i s t er are p l aced i n t he s a m e m e m or y area. t her e f ore, s a m e i n s t ruc t i on s enab l e bo t h d a t a t ran s f e r and operat i on w i t hout t he need t o d i s t i ngu i s h m e m o r y and i/ o. t he progr a m coun t e r o f g ms81508 / 16 con s i s t s of 16-bit and m e m o r y addre ss i ng s p ace i s 64k by t e . 2.2.1. r a m area ram( i n c l ude s s t ack area) i s 448 b y t e s ( 0000 h 01 f f h ). t he i n t e rnal r am i s u s ed f o r da t a s t orage, s ubrou t i ne call i ng or s t ac k area w hen i n t e rrup t s occur. w he n ram i s u s ed a s t he s t ack area, t he dep t h o f t he s ubrou t i n e " ne s t i ng" and t h e i n t e rrupt l e v e l s s hou l d be kept i n m i n d i n order t o a v o i d de s t ruct i on o f t he r a m con t en t s . 2.2.2 . p er i p her a l r e g i ster a rea addres s 00c0 h 00 f f h are a ss i gned f o r pe r i pheral reg i s t er. 2.2.3 . p rogra m ro m area pcall s ubrou t i ne s m u s t b e l o ca t e d i n pc a ll area ( f f 00 h f f b f h ). t c a ll v e c t or are a ( f f c0 h ff d f h ) ha s t h e v e c t or addre s s corre s p o nd i ng t o t call i n s t r u c ti o n . i n t e rr up t v e c to r are a ( f f e0 h f f ff h ) ha s t h e v e c t or addre s s of i n t errup t s , i n c l u s i v e r e set.
GMS81508/16 13 ram (192 byte) peripheral registers ram(stack) (256 byte) program rom pcall area tcall vector area interrupt vector area !0000h !00c0h !0100h !0200h !c000h !e000h !ff00h !ffc0h !ffe0h not used area 0-page 1-page direct page(dp) u-page g m s 8 1 5 0 8 g m s 8 1 5 1 6 absolute address vector table tcall interrupt address vector address vector ffc0h - ffc1h tcall 15 ffe0h - ffe1h not used ffc2h - ffc3h tcall 14 ffe2h - ffe3h not used ffc4h - ffc5h tcall 13 ffe4h - ffe5h serial i/o ffc6h - ffc7h tcall 12 ffe6h - ffe7h basic interval timer ffc8h - ffc9h tcall 11 ffe8h - ffe9h watch dog timer ffcah - ffcbh tcall 10 ffeah - ffebh a/d converter ffcch - ffcdh tcall 9 ffech - ffedh timer 3 ffceh - ffcfh tcall 8 ffeeh - ffefh timer 2 ffd0h - ffd1h tcall 7 fff0h - fff1h timer 1 ffd2h - ffd3h tcall 6 fff2h - fff3h timer 0 ffd4h - ffd5h tcall 5 fff4h - fff5h ext. int. 3 ffd6h - ffd7h tcall 4 fff6h - fff7h ext. int. 2 ffd8h - ffd9h tcall 3 fff8h - fff9h ext. int. 1 ffdah - ffdbh tcall 2 fffah - fffbh ext. int. 0 ffdch - ffddh tcall 1 fffch - fffdh not used ffdeh - ffdfh tcall 0 fffeh - ffffh reset
hyundai microelectronics 14 2.2.4 . p er i p her a l r e g i ster l i st a d d ress re g i ster name s y m b o l r / w reset value 7 6 5 43 2 10 00 c 0 h r 0 port da t a reg i s t er r0 r / w u n d e f i n ed 00 c 1 h r 0 port i/ o d i rec t i on reg i s t er r 0 dd w 0 0 0 00 0 00 00 c 2 h r 1 port da t a reg i s t er r0 r / w u n d e f i n ed 00 c 3 h r 1 port i/ o d i rec t i on reg i s t er r 0 dd w 0 0 0 00 0 00 00 c 4 h r 2 port da t a reg i s t er r0 r / w u n d e f i n ed 00 c 5 h r 2 port i/ o d i rec t i on reg i s t er r 0 dd w 0 0 0 00 0 00 00 c 6 h r 3 port da t a reg i s t er r0 r / w u n d e f i n ed 00 c 7 h r 3 port i/ o d i rec t i on reg i s t er r 0 dd w 0 0 0 00 0 00 00 c 8 h r 4 port da t a reg i s t er r4 r / w u n d e f i n ed 00 c 9 h r 4 port i/ o d i rec t i on reg i s t er r 4 dd w 0 0 0 00 0 00 00 c a h r 5 port da t a reg i s t er r5 r / w u n d e f i n ed 00 c b h r 5 port i/ o d i rec t i on reg i s t er r 5 dd w 0 0 0 0 0 0 0 0 00 c c h r 6 port da t a reg i s t er r6 r / w u n d e f i n ed 00 c d h r 6 port i/ o d i rec t i on reg i s t er r 6 dd w 0 0 0 0 - - - - 00 d 0 h port r 4 m o d e reg i s t er p m r 4 w 0 0 0 00 0 00 00 d 1 h port r 5 m o d e reg i s t er p m r 5 w - - 0 0 - - - - 00 d 2 h t est m o de re g is t er t m r w - - - - - 0 0 0 00 d 3 h basic in t erval re g is t er b i t r r u n d e f i n ed c l ock con t ro l r eg i s t er ckc t l r w - - 0 10 1 11 00 e 0 h w a t ch dog t i m er w d tr w - 0 1 11 1 11 00 e 2 h t i m e r m ode re g i s t er 0 t m 0 r / w 0 0 0 00 0 00 00 e 3 h t i m e r m ode re g i s t er 2 t m 2 r / w 0 0 0 00 0 00 00 e 4 h t i m er 0 da t a reg i s t er t d r 0 r / w u n d e f i n ed 00 e 5 h t i m er 1 da t a reg i s t er t d r 1 r / w u n d e f i n ed 00 e 6 h t i m er 2 da t a reg i s t er t d r 2 r / w u n d e f i n ed 00 e 7 h t i m er 3 da t a reg i s t er t d r 3 r / w u n d e f i n ed 00 e 8 h a / d conver t e r m ode reg i s t er a d cm r / w - - 0 00 0 01 00 e 9 h a / d conver t er d a t a reg i s t er a d r r u n d e f i n ed 00 e a h seri a l i/o m o d e re g is t er si o m r / w - 0 0 00 0 01
g m s 81508/16 15 a d d ress re g i ster name s y m b o l r / w reset value 7 6 5 43 2 10 00 e b h seri a l i/o re g is t er si o r r/w u n d e f i n ed 00 e c h buzzer driver re g is t er b u r w u n d e f i n ed 00 f 0 h p w m 0 da t a reg i s t er pw m r0 w u n d e f i n ed 00 f 1 h p w m 1 da t a reg i s t er pw m r1 w u n d e f i n ed 00 f 2 h p w m con t ro l reg i s t er pw m cr w 0 0 00 f 3 h i n t errupt m ode r eg i s t er i m o d r / w - - 0 00 0 00 00 f 4 h i n t errupt enab l e reg i s t er l o w i e n l r / w 0 0 0 0 - - -- 00 f 5 h i n t errupt request f l ag reg i s t er l o w i r q l r / w 000 0---- 00 f 6 h i n t errupt enab l e reg i s t er h i gh i e n h r / w 0 0 0 00 0 00 00 f 7 h i n t errupt request f l ag reg i s t er h i gh i r q h r / w 0 0 0 00 0 00 00 f 8 h e x t . i n t errupt edge s e l ec t i on re g i s t er i e d s w 0 0 0 00 0 00 -: not u s ed w r i t e o n l y reg i s t er can n o t b e accessed by b i t m an i p u l a t i on i n s t ruct i o n .
hyundai microelectronics 16 2.3. c l ock gener a t i on c i rc u i t t he c l ock generat i on c i rc u i t o f g ms81508 / 16 con s i s t s of o s cil l at i on c i rc u i t, pre s ca l e r, ba s i c i n t e r v a l t i m e r. t he s ource c l oc k o f pe r i phera l s i s pr o v ided by 11-bit pre s ca l e r. o s c c i r c u it c l o ck p u l s e g e ne r a t or p r e s ca l er m u x b. i .t . ( 8 ) w . d . t . ( 6 ) c o m p a r a t o r w d tr 0 1 2 3 4 5 6 7 i n ter n a l s y s t e m c l o ck i f bit i f wdt b t cl en p c k w d t cl to r e s et c i r c u it i n ter n a l data b u s 8 6 6 ckc t lr 6 2.3.1. oscil l a t i o n circ u i t t he c l ock s i gna l i nc o m i n g f r o m cry s t al o s c i l l a t o r or cerami c re s ona t or v i a x i n an d x out or f r o m e x t e rn a l c l oc k v ia x i n i s s upp li ed t o c l oc k p u l s e g enera t or and pre s ca l e r. t he i n t ernal s y s t e m c l ock f or cp u i s m ade b y c l o c k pu l s e g enera t or, and s e v eral per i pheral c l ock i s di v ided by pre s ca l er. t he c l ock generat i on c i rc u i t o f c r y s t al o s cil l a t or o r ceramic re s ona t or i s s ho w n i n be l o w . c r y s t al o s ci l l a t or or cer a m i c re s ona t or e x t e r n a l c l o ck i n s t op mode, t he o s cil l at i o n i s s t opped, x i n p i n goe s t o " l " l e v el s t a t u s , and x out p i n goe s t o " h " l e v e l s t a t e. x i n c i n gnd cout x out x i n ex t e rnal c l ock o pen x out
GMS81508/16 17 2.3.2. prescaler the prescaler consists of 11-bit binary counter, and input clock is supplied by oscillation circuit. the frequency divided by prescaler is used as a source clock for peripherals. frequency-divided outputs of prescaler f ex ( ) ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 interval 4 2 1 500 250 125 62.5 31.25 15.36 7.18 3.59 period 250 500 1 2 4 8 16 32 64 128 256 the peripheral clock supplied from prescaler can be stopped by enpck. (however, ps11 cannot be stopped by enpck) wwwwww 76543210 8 internal data bus peripherals enpck f ex b.i.t. ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 8 ps0 enable peripheral clock 0 : stop 1 : supply enpck wdton btcl bts2 bts1 bts0 ckctlr <00d3 h >
hyundai microelectronics 18 2.4. basic i n t er v a l t i m er t he ba s i c i n t e r v a l t i m e r(b. i . t . ) ha s 8-b i t b i nary coun t er. t he opera t i on s i s s ho w n be l o w . . g enera t e s re f e renc e ti m e i n t e r v a l i n t e r rupt reque s t a s a t imer. . t he count i n g v a l ue o f b . i . t. can b e read. ( no t e; t h e w r i t i ng at s a m e addre s s o v er w r i t e s t he ck c t lr . ) . t he o v e r f l o w of b. i .t be u s ed t he s ource c l oc k o f w a tch dog ti m e r . 2.4.1 . contr o l of b a s i c i nterv a l t i m er t h e ba s i c i n t e r v a l t i m e r i s f re e runn i ng ti m e r. w hen t h e count i ng v a l u e i s change d " 0 f f h" t o " 00h" , t h e i n t e rrupt reque s t f l a g i s genera t ed. t h e coun t er can b e c l eared b y s e tt i ng b t c l ( b i t 3 of ckc t lr ) and t he b t c l i s au t o-c l eared a ft er 1 m ach i n e cy c l e. t h e i nit i al s t a t e ( a ft er re s e t ) o f btcl i s 0 . t he i nput c l ock o f ba s i c i n t e r v a l ti m er i s s e l ec t ed by b t s 2 ~ b t s0 ( b i t 2 ~ 0 o f ck c t lr) a m ong t he pre s ca l e r ou t pu t s (ps4 ~ ps11 ) . t he ba s i c i n t e r v a l t i m e r reg i s t er ( bi t r) can b e read. t he ckc t lr an d t he b i t r h a v e a s a m e addre ss (00d3h). so, if you w ri t e t o t h i s addres s , t he ckc t lr w ou l d be con t rol l ed. if you rea d t h i s addre s s , t he coun t i n g v a l ue o f bi t r w ou l d be read. c l o ck c o n t r o l reg i s t er ps4 w d t o n e n p c k b t cl b t s2 b t s1 b t s0 ckc tl r bi t 7 bi t 6 bi t 5 bi t 4 bi t 3 bi t 2 bi t 1 bi t 0 bi t r ps5 ps6 ps7 ps8 ps9 ps 1 0 ps 1 1 mux ifbit i n t e r n a l d a t a b u s i n t e r n a l d a t a b u s s a m e a d d r e s s w h en r ea d , it c a n b e r e a d as c ou n t e r v a l u e . w hen w r i t e, it c a n b e w r i t e a s c ont r ol r egi s t e r . b.i. t . i n p ut c l o c k s e l e c t i on b.i. t . c lear ( w he n w r it i ng ) 0 : b.i. t . f r ee-r u n 1 : b.i. t . c l ear ( a u t o c l ea r ed a f t er 1 m a c h i n e c y c l e ) 7 6 5 4 e n p c k w d t o n 3 b t c l 2 b t s2 1 b t s1 0 b t s0 w w w w w w < 00d3 h > ckc tl r
GMS81508/16 19 basic interval timer data register 2.5. watch dog timer the watch dog timer is a means of recovery from a system problem. in this device, the watch dog timer consists of 6-bit binary counter, 6-bit comparator and watch dog timer register(wdtr). the source clock of wdt is overflow of basic interval timer. the interrupt request of wdt is generated when the counting value of wdt equal to the contents of wdtr( bit0~5). this can be used as s/w interrupt or micom reset signal(watch dog function). 2.5.1. control of watch dog timer it can be used as 6-bit timer or wdt according to bit5(wdton) of clock control register (ckctlr). the counter can be cleared by setting wdtcl ( bit 6 of wdtr) and the wdtcl is auto-cleared after 1 machine cycle. the initial state (after reset) of wdtcl is 0 . clock control register watch dog timer register wdt on 0 : 6-bit timer 1 : watch dog timer 7 6 5 4 enpck wdton 3 btcl 2 bts2 1 bts1 0 bts0 w w w w w w <00d3 h > ckctlr watch dog timer clear 0 : free run 1 : w.d.t counter clear 7 6 wdtcl 5 wdtr5 4 3 2 1 0 w w w w w w w w <00e0 h > wdtr determines the interval of w.d.t interrupt wdtr3 wdtr4 wdtr0 wdtr1 wdtr2 b.i.t data 7 6 5 4 3 2 1 0 r r r r r r r r <00d3 h > bitr
hyundai microelectronics 20 t he i n t e r v al o f w d t i n t e rrupt i s de c i ded by t h e i n t e r rupt i n t e r v a l o f ba s i c i n t e r v a l ti m e r an d t h e con t en t s of w d t r. th e int e r v a l o f w d t = th e c o nt e nt s o f w d t r th e i nt e r v a l o f b . i . t. c a uti o n) d o n o t u s e th e c o nt e nt s o f w d t r = " 0 " t he re l a t i on s h i p be t w een t he i nput c l ock o f b. i .t an d t he ou t put o f w . d. t . ( @ 8mhz) b t s 2 b t s 1 b t s0 b .i . t . i nput c l ock t he cy c l e o f b. i . t . t he cy c l e o f w . d. t . ( m a x) 0 0 0 ps4 ( 2 ) 512 32 , 256 0 0 1 ps5 ( 4 ) 1 , 024 64 , 512 0 1 0 ps6 ( 8 ) 2 , 048 129 , 024 0 1 1 ps7 ( 1 6 ) 4 , 096 258 , 048 1 0 0 ps8 ( 3 2 ) 8 , 192 516 , 096 1 0 1 ps9 ( 6 4 ) 16 , 384 1 , 032 , 192 1 1 0 ps10 ( 12 8 ) 32 , 768 2 , 064 , 384 1 1 1 ps11 ( 25 6 ) 65 , 536 4 , 128 , 768 2.5.2 . the ou t put o f w d t s i gn a l t he o v e r f l o w of w d t can b e ou t put t hrough r54/ w dt o port by s e t t i ng bi t 4 o f pmr5( w d t s ) t o " 1 ". p o r t r5 m o de r e g i s t er < 00d1 h > pmr5 7 - 6 - 5 buzs 4 w d ts 3 - 2 - 1 - 0 - w w r 5 4 / w d t o s e l e cti o n 0 : r 54 ( i n p u t / o u t p ut ) 1 : w d t o ( o ut p ut )
GMS81508/16 21 2.6. timer the GMS81508/16 has four multi-functional 8-bit binary timers(timer0~timer3). timer0 (or timer2) is can be used as a 16-bit timer/event counter with timer1(or timer3). the timer0-1 and timer2-3 have same functions and structures. so, we will explains about timer0 and timer1 only. operation mode of timer timer0,timer2 timer1,timer3 -. 8-bit interval timer -. 8-bit event counter -. 8-bit input capture -. 8-bit interval timer -. 8-bit rectangular pulse output -. 16-bit interval timer -. 16-bit event counter -. 8-bit rectangular pulse output ck ps6 ps4 ps2 t0cn t1st int0 cap0 t0st ps6 ps4 ps2 2 ec0 tdr0 internal data bus 16bit mode 16bit mode mux 8 tm0 7 1 0 3 2 5 4 7 6 tdr1 ift0 intr0 t1o ift1 8 8 comparator 0 8 comparator 1 data reg. 1 data reg. 0 8 t 0 8 t 1 8 8 clea ck clea 1 mux 0 0 mux 1 f / f edge 1 mux 0 mux 2
hyundai microelectronics 22 t i me r m o de r e g i s t e r 0 , 2 ( t m0, t m2) t i me r d a t a reg i s t er ( t dr0 ~ t dr3) t 1 i n p u t c l o c k s e l e c t i o n 0 0 : c o nn e c t i o n t o t 0 ( 1 6 b i t m o d e ) 0 1 : p s 2 ( 5 0 0 ) 1 0 : p s 4 ( 2 ) 1 1 : p s 6 ( 8 ) t 3 i n p u t c l o c k s e l e c t i o n 0 0 : c o nn e c t i o n t o t 2 ( 1 6 b i t m o d e ) 0 1 : p s 2 ( 5 0 0 ) 1 0 : p s 4 ( 2 ) 1 1 : p s 6 ( 8 ) t 0 i n p u t c l o c k s e l e c t i o n 00 : e c 0 0 1 : p s 2 ( 5 0 0 ) 1 0 : p s 4 ( 2 ) 1 1 : p s 6 ( 8 ) t 2 i n p u t c l o c k s e l e c t i o n 00 : e c 2 0 1 : p s 2 ( 5 0 0 ) 1 0 : p s 4 ( 2 ) 1 1 : p s 6 ( 8 ) < 00e2 h > < 00e3 h > t m 0 t m 2 7 7 cap0 cap2 6 6 t 1 s t t 3 s t 5 5 t 1 s l 1 t 3 s l 1 4 4 t 1 s l 0 t 3 s l 0 3 3 t 0 s t t 2 s t 2 2 t 0 c n t 2 c n 1 1 t 0 s l 1 t 2 s l 1 0 0 t 0 s l 0 t 2 s l 0 r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w t 0 s t a r t/s t op c o n t r ol 0 : c o u n t s t op 1 : c o u n t i n g s t a r t a ft er c l ea r i n g t 0 t 2 s t a r t/s t op c o n t r ol 0 : c o u n t s t op 1 : c o u n t i n g s t a r t a ft er c l ea r i n g t 2 t 0 s t a r t/s t op c o n t r ol 0 : count s t o p 1 : count s t a rt t 2 s t a r t/s t op c o n t r ol 0 : count s t o p 1 : count s t a rt in p ut c a p tu r e s e l e c t i on 0 : t i m e r / c ou n t e r 1 : i n put c ap t u r e in p ut c a p tu r e s e l e c t i on 0 : t i m e r / c ou n t e r 1 : i n put c ap t u r e t 1 s t a r t/s t op c o n t r ol 0 : c o u t s t op 1 : c o u n t i n g s t a r t a ft er c l ea r i n g t 1 t 3 s t a r t/s t op c o n t r ol 0 : c o u t s t op 1 : c o u n t i n g s t a r t a ft er c l ea r i n g t 3 t dr0~3 7 6 5 4 3 2 1 0 r / w r / w r / w r / w r / w r / w r / w r / w ( w ri t e) m od u l o d a t a w r ite ( read ) c o u n t v a l u e r ead < 00e4 h~ 00e7 h >
GMS81508/16 23 2.6.1. control of timer t0 ( t1 ) consists of 8-bit binary up-counter. when the counting value of timer0 , timer1 and timer0-1(16bit) become equal to the contents of timer data register(tdr0,tdr1,tdr0-1) value, the counter is cleared to "00h" and restarts count-up operation. at this time, interrupt request (ift0 or ift1) is generated. any of the ps2, ps4, ps6 or external clock can be selected as the clock source of t0 by bit1(t0sli) and bit0(t0sl0) of tm0. any of the ps2, ps4, ps6 or overflow of t0 can be selected as the clock source of t1 by bit5(t1sl1) and bit4(t1sl0) of tm0. when the overflow of t0 is selected as input clock of t1, timer0-1 operates as 16 -bit timer. in this case, timer0-1 only is controlled by t0st,t0cn and the interrupt vector is timer0 vector. the operation of t0, t1 is controlled by bit3(t0st), bit2(t0cn) and bit6(t1st) of tm0. t0cn controls count stop/start without clearing counter. t0st and t1st control count stop/start after timer clear. in order to enable count-up of timer , t0cn, t0st and t1st should become 1 . in order to start count-up after clearing of counter, t0st or t1st should be set to "1" after set to "0" temporarily. interval period interrupt interrupt interrupt match match match clear clear clear 00 h ift0 t0 value tdr0 value count count stop count stop 0 1 start 0 1 clear & start interrupt interrupt match match clear clear clear 00 h ift0 t0 value tdr0 value t0st counter t0cn
hyundai microelectronics 24 by read ti m e r da t a re g i s t er( t dr0 ~ 3 ) , t he count i n g v alue o f ti m e r can be read at any ti m e . 2.6.2. interv a l t i m er t he i n t e rrupt c y c l e i s de t erm i ned b y t he s ource c l o c k o f ti m e r and t he con t en t s o f t dr. i n terru p t cyc l e = s o u rce c l o c k t h e c ont e n t s of t d r i n order t o w r i t e da t a t o t dr, yo u h a v e t o s t op ti m e r . o t her w i s e, t d r v a l u e i s i n v a l i d. maxi m u m i n t errupt cy c l e a c cord i n g t o s ource c l oc k @ f e x = 8mhz 8-b i t t ime r mode 16-b i t t i m er mode s ource c l ock m a x. count s ource c l ock m a x. count ps2 ( 0. 5 ) 12 8 ps2 ( 0. 5 ) 32 , 76 8 t 0 ,t2 ps4 ( 2 ) 512 ps4 ( 2 ) 131 , 072 ps6 ( 8 ) 2 , 048 ps6 ( 8 ) 524 , 288 ps2 ( 0. 5 ) 12 8 t 1 ,t3 ps4 ( 2 ) 512 ps6 ( 8 ) 2 , 048 2.6.3. e ven t counter t he e v e n t coun t e r opera t e s i n t he s a m e w a y a s t he i n t e r v a l ti m e r e xcept i t coun t s t he e x t e rn a l e v ent i nput f r o m r44 / ec0 and r45 / ec1 po r t . it o n l y coun t s at t h e f a ll i ng edge o f e v ent i nput c l ock. i n order t o i nput o f e x t ernal e v e n t c l oc k , t h e re l e v ant port mode reg i s t er( b i t 4 , b i t 5 o f p mr4) i s s et t o " 1 " . t d r v a l ue s hou l d b e i n i t i al i ze d t o f f h becau s e ti m e r i s c l eared w hen i t equa l s t o t dr v a l ue, but if you w ant t o u s e i n t errupt, t d r v a l ue s hou l d be w r i t t e n t o " 1 h ~ f f h " . 2.6.4 . p u l se ou t put a pu l s e w i d t h 50% cy c l e duty i s ou t put t o t he r46/ t 1 o or r47/ t 3 o port and r e v e r s e t he ou t put w h e n t i m e r i n t e rrupt i s genera t ed. t h i s crea t e s a pu l s e per i od w h i c h i s t w o t i m e s t h a t o f t h e t i m e r i n t e rrupt cy c l e . t he ou t put pu l s e per i o d i s de t e r m i ned by t he s ource c l oc k o f t imer and t h e con t en t s of t dr. ou t pu t p e r i o d = s o u r c e c l o ck ( ) t h e c o nte n ts o f t d r 2 i n o r d e r t o ou t p u t o f p u l s e , t h e b i t 6 , b i t 7 o f pm r 4 i s s e t t o " 1 ". 2.6.5. inpu t cap t ure t h i s f unct i o n m ea s ure s t he per i od or w i d t h o f p u l s e i nput f r o m e x t e rnal i nt. (r40/ i n t 0 , r42 / i n t 2 ) por t . t he per i od o f pu l s e i s m ea s ured by s e l e c t i ng r i s i ng edge or f a l l i n g edge o f t h e i n t e rrupt edge s e l e ct reg i s t er( i e d s) an d t he w i d t h o f p u l s e i s m ea s ured by s e l e c t i ng bo t h edge o f i eds. t he e x t e rna l i n t e rrupt i s genera t ed at t h e v a l i d edge accord i n g t o ieds. at t h i s t i m e , t he count i n g v a l ue o f ti m er i s l oade d i n t o t dr and coun t e r i s c l eared and re s t ar t s coun t -up.
GMS81508/16 25 r40/int0 or r42/int2 rising edge falling edge both edge period hwidth lwidth timer operation the counting value of timer is latched timer is cleared to 00h timer restart count-up port r4 mode register <00d0 h > pmr4 7 t3s 6 t1s 5 ec2s 4 ec0s 3 int3s 2 int2s 1 int1s 0 int0s w w w w w w w w r44/ ec0 selection 0 : r44 ( input / output ) 1 : ec0 ( input ) r45/ ec2 selection 0 : r45 ( input / output ) 1 : ec2 ( input ) r47 / t3 selection 0 : r47 ( input / output ) 1 : t3 ( output ) r46 / t1 selection 0 : r46 ( input / output ) 1 : t1 ( output ) r40 / int0 selection 0 : r40 ( input / output ) 1 : int0 ( input ) r42 / int2 selection 0 : r42 ( input / output ) 1 : int2 ( input )
hyundai microelectronics 26 2.7. ex t ern a l i n t errupt an i n t e r rupt reque s t i s genera t ed w hen a l e v e l - chang e f r o m " h " t o " l " o r " l " t o " h " o f i n t 0, i n t 1, i n t 2, i n t 3 p i n i s de t ec t ed. t he edge o f e x t ern a l i n t errupt i s s e l ec t ed b y i n t errupt edge s e l ec t i on re g i s t er( i eds ) and por t s (r40 , r41 , r42 , r43) corre s pond i ng t o i n t 0 , i n t 1 , i n t 4 , i n t 3 are de t erm i ned a s a i nput port f o r e x t e rnal i n t e rrupt b y bi t 0 ~ 3 o f por t 4 mode reg i s t er(pmr4 ) . e x t . i n t erru p t e d g e s e l e c t i o n r e g i s t er < 00d0 h > pmr4 7 t 3 s 6 t 1 s 5 ec 2 s 4 ec 0 s 3 i n t 3s 2 i n t 2s 1 i n t 1s 0 i n t 0s w w w w w w w w r 40 / i n t 0 s e l e c t i on 0 : r 40 ( i n p u t / o u t p ut ) 1 : i n t 0 ( i n p ut ) r 43 / i n t 3 s e l e c t i on 0 : r 43 ( i n p u t / o u t p ut ) 1 : i n t 3 ( i n p ut ) r 41 / i n t 1 s e l e c t i on 0 : r 41 ( i n p u t / o u t p ut ) 1 : i n t 1 ( i n p ut ) r 42 / i n t 1 s e l e c t i on 0 : r 42 ( i n p u t / o u t p ut ) 1 : i n t 2 ( i n p ut ) < 00 f 8 h > i e d s 7 ied3h 6 ied 3 l 5 ied2h 4 ied 2 l 3 ied1h 2 ied 1 l 1 ied0h 0 ied 0 l w w w w w w w w in t 0 e d g e s e l e c t i on 0 0 : - 0 1 : f a l li n g 1 0 : r i s i ng 1 1 : f a l li n g & r i s i ng in t 1 e d g e s e l e c t i on 0 0 : - 0 1 : f a l li n g 1 0 : r i s i ng 1 1 : f a l li n g & r i s i ng in t 3 e d g e s e l e c t i on 0 0 : - 0 1 : f a l li n g 1 0 : r i s i ng 1 1 : f a l li n g & r i s i ng in t 2 e d g e s e l e c t i on 0 0 : - 0 1 : f a l li n g 1 0 : r i s i ng 1 1 : f a l li n g & r i s i ng
GMS81508/16 27 2.8. a/d converter a/d converter has an 8-bit resolution, and input is possible up to 8 channel. a/d converter consists of analog input multiplexer, a/d convert mode register, resistance ladder, sample and holder, successive approximation circuit and a/d conversion data register. ladder resistor decoder mux s/h control register successive approximation circuit a/d conversion data register(8bit) aden ads2 ads1 ads0 adst adsf - - an0 an1 an2 an3 an4 an5 an6 an7 comparator avref avss internal data bus ifa 2.8.1. control of a/d converter the analog input is selected by bit2~4 of a/d converter mode register(adcm). this bits chooses among an0~an7. the other analog pins which are not used not a/d conversion be used as normal port. the a/d conversion is started by setting a/d conversion start bit (adst) to "1"(only for aden=1). after a/d conversion is started, adst is cleared by hardware. during a/d conversion, when adst is set to "1", a/d conversion starts again from the beginning. the analog input voltage and the reference voltage are compared and the result is stored in the a/d converter data register(adr) and adsf(bit0 of adcm) is set to "1". the a/d interrupt request is generated at the completion of a/d conversion. the result of the conversion is obtained by reading out the a/d register(adr).
hyundai microelectronics 28 a / d c o nve r t e r m o d e r e gi s t er( a dcm) a / d c o nve r t e r d a t a re g i s t er( a dr) < 00e8 h > a d c m 7 6 5 4 ads2 aden 3 ads1 2 ads0 1 adst 0 adsf - - r / w r / w r / w r / w r / w r / w a /d c o n ve r s i on s t atus b i t 0 : du r i n g a /d c o n ve r s i on 1 : c o m p l e t e d a /d c o n ve r s i on a/d c o n ve r t e r i n p u t s e l e c t 0 0 0 : c h an n e l 0 ( a n 0) 0 0 1 : c h an n e l 1 ( a n 1) 0 1 0 : c h an n e l 2 ( a n 2) 0 1 1 : c h an n e l 3 ( a n 3) 1 0 0 : c h an n e l 4 ( a n 4) 1 0 1 : c h an n e l 5 ( a n 5) 1 1 0 : c h an n e l 6 ( a n 6) 1 1 1 : c h an n e l 7 ( a n 7) a /d c o n ve r t e r e n a b l e b i t 0 : d i s a b l e a/d c o n v e r t er 1 : e n a b l e a /d c o n ve r t e r a /d c o n ve r s i on s t a r t bit 0 : i n v a lid 1 : s t a r t a / d c o n ve r s i on ( a ft e r 1 c y c l e , b e c l ea r ed t o " 0 " ) < 00e8 h > a d c m 7 6 5 4 ads2 aden 3 ads1 2 ads0 1 adst 0 adsf - - r / w r / w r / w r / w r / w r a /d c o n ve r s i on s t atus b i t 0 : du r i n g a /d c o n ve r s i on 1 : c o m p l e t e d a /d c o n ve r s i on a/d c o n ve r t e r i n p u t s e l e c t 0 0 0 : c h an n e l 0 ( a n 0) 0 0 1 : c h an n e l 1 ( a n 1) 0 1 0 : c h an n e l 2 ( a n 2) 0 1 1 : c h an n e l 3 ( a n 3) 1 0 0 : c h an n e l 4 ( a n 4) 1 0 1 : c h an n e l 5 ( a n 5) 1 1 0 : c h an n e l 6 ( a n 6) 1 1 1 : c h an n e l 7 ( a n 7) a /d c o n ve r t e r e n a b l e b i t 0 : d i s a b l e a/d c o n v e r t er 1 : e n a b l e a /d c o n ve r t e r a /d c o n ve r s i on s t a r t bit 0 : i n v a lid 1 : s t a r t a / d c o n ve r s i on ( a ft e r 1 c y c l e , b e c l ea r ed t o " 0 " ) < 00e9 h > a d r 7 6 5 4 3 2 1 0 r r r r r r r r a /d c o n ve r s i on d a t a
GMS81508/16 29 2.9. serial i/o the serial i/o is 8-bit clock synchronous type and consists of serial i/o register, serial i/o mode register, clock selection circuit octal counter and control circuit. sior 1 0 3 2 5 4 7 6 sclk octal counter control circuit internal data bus internal data bus sm0 sm1 srdy srdy0 srdy in 2 mux ps5 ps4 ps3 ifsio exclk r q s sin sout 8 6 6 7 0 siom sm0 sosf siost sck0 sck1 srdy sm1
hyundai microelectronics 30 s e r ial i /o m ode register t h i s reg i s t er co n t ro l s s e r i al i / o f unct i on. accor d i ng t o sck1 and sck 0 , t h e i n t e rn a l c l oc k or e x t e rn a l c l oc k can be s e l e c t ed. s e r ial i /o data regis t er t he se r i al i /o d a t a reg i s t er ( s i or ) i s a 8-bit s hi f t re g i s t er. f i r s t l s b i s s end or i s recei v ed. < 00eb h > s i or 7 d7 6 d6 5 d5 4 d4 3 d3 2 d2 1 d1 0 d0 r / w r / w r / w r / w r / w r / w r / w r / w a t t r an s mi t t i on s e n d i n g d a t a a t s e n d in g m o de r e c e i v i n g d a t a a t r e c e i v in g m o de < 00ea h > s i o m 7 6 sr d y 5 s m 1 4 s m 0 3 sck1 2 sck0 1 si o st 0 si o sf r / w r / w r / w r / w r / w r / w r s e r i al t r an s m i s s i on c l o c k s e l e c t i on 0 0 : p s 3 ( 1 ) 0 1 : p s 4 ( 2 ) 1 0 : p s 5 ( 4 ) 1 1 : e x t e r n al c l o c k s e r i al o p e r a t i o n m o d e 0 0 : n o r m al p o r t ( r 5 2, r 51 , r 5 0) 0 1 : s e n d i n g m o d e ( s cl k , s o u t , r 5 0 ) 1 0 : r e c e i v i n g m o d e ( s c l k, r 51 , s i n) 1 1 : s e n d i n g & r e c e i v i ng m d ( s l k s s i) s e r i al t r an s m i ss i on s t a r t 0 : i n va l i d 1 : s t a r t(a f t e r o n e sck, b e c o m e s 0) s e r i al t r an s m i ss i on s t a t us f l ag 0 : du r i n g t r an s mi s s i on 1 : f i ni s h ed r 53 / s r d y s e l e c t i o n 0 : r 5 3 1 : s r d y
GMS81508/16 31 2.9.1. data transmission/receiving timing the serial transmission is started by setting siost(bit1 siom) to 1 . after one cycle of sck, siost is cleared automatically to 0 . the serial output data from 8-bit shift register is output at falling edge of sclk. and input data is latched at rising edge of sclk. when transmission clock is counted 8 times, serial i/o counter is cleared as 0 . transmission clock is halted in h state and serial i/o interrupt (ifsio) occurred. timing diagram of serial i/o 2.9.2. the serial i/o operation by srdy pin transmission clock = external clock the srdy pin becomes "l" by siost = "1". this signal tells to the external system that this device is ready for serial transmission. the external system detects the "l" signal and starts transmission. the srdy pin becomes "h" at the first rising edge of transmission clock. transmission clock = internal clock the i/o of srdy pin is input mode. when the external system is ready to for serial transmission, the "l" level is inputted at this pin. at this time this device starts serial transmission. siost srdy(output) siost srdy(input) d7 d6 d5 d1 d4 d3 d2 d0 d7 d6 d5 d1 d4 d3 d2 d0 input clock sclk latch output ifsio sin sout siost
hyundai microelectronics 32 2.9.3 . the m ethod of s e r i a l i/o se l ect t ran s m i ss i on / recei v in g m ode < not i ce > w hen e x t e rnal c l o c k i s u s ed, t h e f requency s hou l d be l e s s t han 1mhz and recom m ended du t y i s 50%. i n ca s e of s end i n g m ode, w r i t e d a t a t o b e s end t o si o r. s e t s io s t t o 1 t o s t art s e r i a l t ran s m i s s i on. < not i c e > if bo t h t ran s m i s s i o n m ode i s s e l e c t ed an d t ran s m i s s i on i s per f o r m e d s i m u l t aneou s l y i t w ou l d b e m ade error. t he sio i n t e rrupt i s genera t ed at t he c o m p l e t i on o f s i o an d si o sf i s s e t t o 1 . i n s io i n t e rrupt s e r v i ce rout i ne, correct t ran s m i s s i on s hou l d be t e s t ed.
i n ca s e of rec e i v i n g m ode, t he rece i v e d da t a i s acqu i red by read i ng t h e si o r. 2.9.4 . the m ethod t o te s t cor r ect t rans m i ss i o n w i t h s / w s e rial i/o i n t erru p t s e r v i ce routine s i o sf s e =0 wri t e s i o m n o r m al o p e r a t i o n o v e r run e r ror sr a bnormal 0 0 1 1 ser i al me t h od t o t est t r a n sm i ssi o n. note) se : i n t errupt ena b l e reg i s t lo w ien l ( b it3 ) s r : i n t errupt reque s t f l ag reg i s t lo w ir q l ( bit 3 )
g m s 81508/16 33 2.10. p wm p w m ( pu l s e w id t h modu l at i on) ha s a 8-bit re s o l u t i on and t h e ps8 , p s9 , ps10,ps11 o f t he pre s ca l e r can be s e l e c t ed a s i nput c l oc k p w m. pw m r 0 c o m p arat o r c o u n t e r pw m r 1 c o m p arat o r c o u n t e r p1 c k 1 p1 c k 0 p0 c k 1 p0 c k 0 e n 1 e n 0 p o l 1 p o l 0 s q r s q r mux mux p o la r ity p o la r ity p s 8 p s 9 p s 10 p s 11 p s 8 p s 9 p s 10 p s 11 i n t e r n a l d a t a b u s i n t e r n a l d a t a b u s o v e r f l o w o v e r f l o w p w m 0 p w m 1 pw m c r 2.10.1 . contr o l s of p w m t he i nput c l ock i s s e l ec t ed by p w m con t r o l reg i s t er (p w m cr), and t he w i d t h o f pu l s e i s de t erm i ned by t he p w m reg i s t er ( p w mr ) . t he pu l s e per i od accor d i ng t o i nput c l ock are a s f o l l o w s . in p ut c l o c k p w m per i od ps8 ( 32 ) 8 , 1 9 2 ps9 ( 64 ) 16 , 3 8 4 p s 1 0 ( 1 28 ) 32 , 7 6 8 p s 1 1 ( 2 56 ) 65 , 5 3 6 b i t 2 (en0) and b i t 3 (en1) o f p w m con t rol reg i s t er (p w m cr ) de t e r m i ne t h e opera t i on channel o f p w m . w hen en0 = 0 and en1 = 0, p w m doe s not e x ecu t ed. t h e en0 and en1 are ena b l e b i t o f p w m channel 0 and channel 1 re s pec t i v e l y . w hen en0 = 1 , p w m channe l 0 e x ecu t e s . w hen en1 = 1 , p w m channe l 1 e x ecu t e s . p o lo and p o l1 ar e a po l a r i t y control bit o f channe l 0 and channe l 1. w he n t hey are 0, l o w ac t i v e . w he n 1, h i g h a cti v e. p w m cr bec o m e s " 00h" i n re s et s t a t e.
hyundai microelectronics 34 pwm c o n t rol r e g i s t er pwm d a t a re g i s t er (a) ac t i v e low per i o d (b) ac t i v e h i gh per i o d pu l s e w i d t h pu l s e w i d t h c o u n t e r lo a d v a l u e + 1 d u t y c yc l e = 100[ % ] 2 5 6 < 00 f 2 h > pwmcr 7 pick1 6 pick0 5 p 0 ck 1 4 p 0 ck 0 3 en1 2 en0 1 p o l 1 0 p o l 0 w w w w w w w w p w m e n ab l e f l ag 0 0 : d i s ab l e 0 1 : p w m0 1 0 : p w m1 11 : p w m 0, p w m 1 p w m 1 c l o c k s e l e cti o n 0 0 : p s 8 0 1 : p s 9 1 0 : p s 10 1 1 : p s 11 p w m 0 c l o c k s e l e cti o n 0 0 : p s 8 0 1 : p s 9 1 0 : p s 10 1 1 : p s 11 p w m0 o u t put p o l a r i t y 0 : a c t i v e l ow 1 : a c t i v e h i g h p w m1 o u t put p o l a r i t y 0 : a c t i v e l ow 1 : a c t i v e h i g h < 00 f 0 h > < 00 f 1 h > pwmr0 pwmr1 7 6 5 4 3 2 1 0 w w w w w w w w p w m d a t a
GMS81508/16 35 2.11. buzzer driver buzzer driver consist of 6 bit binary counter, buzzer register(bur), and selector of clock. the wide range frequency(500hz~250khz) can be generated using programmable counter. port r55 is assigned for output port of buzzer driver by setting bit5 of pmr5($00d1h) to "1". buck1 buck0 bu5 bu4 bu3 bu2 bu1 bu0 mux 0 1 2 3 4 5 t q ps4 ps5 ps6 ps7 6 buzzer output 6bit counter wtbur internal data bus port r5 mode register buzzer data register <00d1 h > pmr5 7 - 6 - 5 buz 4 wdto 3 - 2 - 1 - 0 - w w r55 / buz selection 0 : r55 ( input / output ) 1 : buz ( output ) <00ec h > bur 7 buck1 6 buck0 5 bu5 4 bu4 3 bu3 2 bu2 1 bu1 0 bu0 w w w w w w w w buzzer count data buzzer source clock selection 00 : ps4 01 : ps5 10 : ps6 11 : p s 7
hyundai microelectronics 36 2.11.1 . b uzzer d r i ver o per a tion t he bi t 0-5 o f buzzer re g i s t er (bur) de t e r m i ne s ou t put f requency f o r buzzer d r i v ing. t h e f requency i s ca l c u l a t ed a s s h o w n be l l o w s . n = b u r da t a f req. = 1 / ( s ource c l oc k 5 n 5 2) t he bi t 6 and bi t 7 o f buzze r reg i s t er (bur ) s e l ec t s t he s ource c l o c k o f t he buzze r coun t er a m ong ps4 (2u s ), ps5 (4u s ), p s6 (8u s ) and ps7 (16u s ). t he buzzer coun t e r i s c l eared by w t s i gnal o f bur and s t ar t s t h e coun t i ng. a l s o , it i s c l eared by coun t er o v e r f l o w , and cont i nue s coun t -up t o ou t put t he r e c t angu l ar w a v e o f duty 50%. * cau t i on: don't u s e bur reg i s t er a s 00h. (coun t e r re s et s t a t e) t he ou t put f requency o f buzze r accor d i ng t o buzzer reg i s t er b i t 5 - b i t 0 ( f e x = 8 mhz) re g . re g . o utput fre q uenc y [ kh z ] re g . re g . o utput fre q uenc y [ kh z ] l o ad dec l o ad hex ps4 ( 2u s ) ps5 ( 4u s ) ps6 ( 8u s ) ps7 ( 16u s ) l o ad dec l o ad hex ps4 ( 2u s ) ps5 ( 4u s ) ps6 ( 8u s ) ps7 ( 16u s ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 250 125 83 . 333 62 . 5 50 41 . 666 35 . 714 31 . 25 27 . 778 25 22 . 728 20 . 834 19 . 23 17 . 858 16 . 666 15 . 626 14 . 706 13 . 888 13 . 158 12 . 5 11 . 904 11 . 364 10 . 87 10 . 416 10 9 . 616 9 . 26 8 . 928 8 . 62 8 . 334 8 . 064 7 . 812 125 62 . 5 41 . 666 31 . 25 25 20 . 834 17 . 858 15 . 626 13 . 888 12 . 5 11 . 364 10 . 416 9 . 616 8 . 928 8 . 334 7 . 812 7 . 352 6 . 944 6 . 579 6 . 25 5 . 952 5 . 682 5 . 434 5 . 208 5 4 . 808 4 . 630 4 . 464 4 . 310 4 . 166 4 . 032 3 . 906 62 . 5 31 . 25 20 . 834 15 . 626 12 . 5 10 . 416 8 . 928 7 . 812 6 . 944 6 . 25 5 . 682 5 . 682 4 . 808 4 . 464 4 . 166 3 . 906 3 . 676 3 . 472 3 . 288 3 . 124 2 . 976 2 . 840 2 . 718 2 . 604 2 . 5 2 . 404 2 . 314 2 . 232 2 . 156 2 . 084 2 . 016 1 . 954 31 . 25 15 . 626 10 . 416 7 . 812 6 . 25 5 . 208 4 . 464 3 . 906 3 . 472 3 . 126 2 . 84 2 . 604 2 . 404 2 . 232 2 . 084 1 . 9541 1 . 838 1 . 736 1 . 644 1 . 562 1 . 488 1 . 420 1 . 358 1 . 302 1 . 250 1 . 202 1 . 158 1 . 116 1 . 078 1 . 042 1 . 008 0 . 976 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 7 . 576 7 . 352 7 . 142 6 . 944 6 . 756 6 . 578 6 . 41 6 . 3 6 . 098 5 . 952 5 . 814 5 . 682 5 . 556 5 . 434 5 . 32 5 . 208 5 . 102 5 4 . 902 4 . 808 4 . 716 4 . 63 4 . 546 4 . 464 4 . 386 4 . 31 4 . 238 4 . 166 4 . 098 4 . 032 3 . 968 3 . 788 3 . 676 3 . 571 3 . 472 3 . 378 3 . 289 3 . 205 3 . 125 3 . 049 2 . 976 2 . 907 2 . 841 2 . 778 2 . 717 2 . 660 2 . 604 2 . 551 2 . 5 2 . 451 2 . 404 2 . 358 2 . 315 2 . 273 2 . 232 2 . 193 2 . 155 2 . 119 2 . 083 2 . 049 2 . 016 1 . 984 1 . 894 1 . 838 1 . 786 1 . 736 1 . 689 1 . 645 1 . 602 1 . 563 1 . 524 1 . 488 1 . 453 1 . 421 1 . 389 1 . 359 1 . 33 1 . 302 1 . 276 1 . 25 1 . 225 1 . 202 1 . 179 1 . 157 1 . 136 1 . 116 1 . 096 1 . 078 1 . 059 1 . 042 1 . 025 1 . 008 0 . 992 0 . 947 0 . 919 0 . 893 0 . 868 0 . 845 0 . 822 0 . 801 0 . 781 0 . 762 0 . 744 0 . 727 0 . 710 0 . 694 0 . 679 0 . 665 0 . 651 0 . 638 0 . 625 0 . 613 0 . 601 0 . 590 0 . 579 0 . 568 0 . 558 0 . 548 0 . 539 0 . 530 0 . 521 0 . 512 0 . 504 0 . 496
GMS81508/16 37 2.12. interrupts the interrupts are usually used when the processing routine has the higher priority than on-going program and a routine muse be executed at specific interval. 2.12.1. interrupt circuit configuration and kinds GMS81508/16 interrupt circuits consists of interrupt enable register (ienh,ienl), interrupt request register (irqh,irql), priority circuit and selecting circuit. the configuration of interrupt circuit is shown in below. 12 irql irqh 4 7 7 0 reset ift3 d ata b us imod 6 i-flag brk to cpu standby mode release priority control t2r t3r ienh 8 1 0 3 2 5 4 7 6 8 4 1 0 3 2 5 4 t0r t1r int2r int3r int0r int1r bitr wdtr sr ar ienl 4 - 5 4 7 6 data bus 4 ift2 ift1 ift0 int3 int2 int1 int0 ifa ifwdt ifbit ifs 8 interrupt vector address gen.
hyundai microelectronics 38 int e rr u pt s ou r c e t he i n t e rrup t s s ource s are e x t e rnal i n t e r rupt s ource( i n t 0, i n t 1 ,i n t 2 ,i n t 3 ), per i pher a l f un c t i on s ource ( t 0 , t 1, t 2 , t 3 , b. i . t ., w .d. t . ,si o , a / dc) and s o f t w are i n t errupt s ource(brk). a f t e r re s e t i npu t (re s e t ) , t h e progr a m i s e x ec u t ed f rom t h e addre s s i n re s e t v e c t or t ab l e l i ke general i n t e r rup t s . t ype ma s k pr i o r i t y i n t e rrupt reque s t source vec t or h vector l non ma s kab l e 1 r s t r e s e t p i n f f f f h f f fe h 2 i n t 0 r e x t ernal i n t e r rupt 0 f f f b h f f fa h 3 i n t 1 r e x t ernal i n t e r rupt 1 f f f 9 h f f f8 h 4 i n t 2 r e x t ernal i n t e r rupt 2 f f f 7 h f f f6 h h / w 5 i n t 3 r e xt e r na l i n t e r r up t 3 f f f5 h f f f4 h interrupt 6 t0r time r 0 f f f3 h f f f2 h 7 t 1 r t i m e r 1 f f f 1 h f f f0 h 8 t 2 r t i m e r 2 ff e f h ff e e h 9 t 3 r t i m e r 3 ffed h f f fc h 1 0 a r a / d c o n v e r t e r f f e b h ff e a h 11 w d t r w a t c h do g ti m e r f f e9 h ffe8 h 1 2 bit r b a s ic i n t e r v a l t i m e r ffe7 h ffe6 h 1 3 s r s e r i a l i / o f f e 5 h ffe4 h s / w i n t e rr u p t n o n ma s kab l e brk b reak in s truc t i on ff d f h ff d e h 2.12.2 . inter r upt con t r o l t he i n t errup t s i s con t r o l l ed by t h e i n t errupt m a s t er enab l e f l ag i -flag(3'rd bit o f p s w ) , i n t errupt enab l e reg i s t er( i enh, i enl), i n t errupt reque s t reg i s t er( i r q h, i r q l ) e x cept r es e t and s /w i n t e rrupt. i n t errupt ena b l e reg i s t er ( ienh, i en l ) t h i s reg i s t er i s c o m po s ed of i n t e rrupt enab l e f lag s of each i n t e rrupt s ource, t h i s f l ag s de t e r m i nes w he t her an i n t e rrupt w i ll be accep t ed or not. w hen enab l e f l a g i s " 0 " , a n i n t e rru p t corre s pond i ng i n t e rrupt s ource i s proh i bi t ed.
GMS81508/16 39 interrupt request flag register ( irqh, irql ) whenever interrupt request is generated, the interrupt request flag is set. the request flag maintains '1" until interrupt is accepted. the accepted interrupt request flag is automatically cleared by interrupt process cycle. interrupt request flag register ( irqh, irql ) is read/ write register. so, it is possible to be checked and changed by program. 2.12.3. interrupt priority when two or more interrupts requests are generated at the same sampling point, the interrupt having the higher priority is accepted. the interrupt priority is determined by h/w. however, multiple priority processing through software is possible by using interrupt control flags(ienh, ienl, i-flag) and interrupt mode register(imod). interrupt masking flag 0 : interrupt disable 1 : interrupt enable <00f6 h > ienh 7 int0e 6 int1e 5 int2e 4 int3e 3 t0e 2 t1e 1 t2e 0 t3e r/w r/w r/w r/w r/w r/w r/w r/w <00f4 h > ienl 7 ae 6 wdte 5 bite 4 se 3 - 2 - 1 - 0 - r/w r/w r/w r/w - - - - interrupt request flag 0 : disable 1 : enable <00f7 h > irqh 7 int0r 6 int1r 5 int2r 4 int3r 3 t0r 2 t1r 1 t2r 0 t3r r/w r/w r/w r/w r/w r/w r/w r/w <00f5 h > irql 7 ar 6 wdtr 5 bitr 4 sr 3 - 2 - 1 - 0 - r/w r/w r/w r/w - - - -
hyundai microelectronics 40 2.12.4. inter r up t s equ e nce w he n i n t e rrupt i s accep t ed, t he on-go i ng proce s s i s s t opped and t he i n t e rrupt s e r v ice rout i n e i s e x ecu t ed. a f t er t he i n t errupt s e r v ice rout i n e i s c o m p l e t e d it i s neces s ary t o re s t ore e v e r y t h i ng t o t he s t a t e be f or e t h e i n t e rrupt occurred. a s s o o n a s an i n t e rrupt i s accep t ed, t he con t en t s o f t he progr a m coun t e r and t he progr a m s t a t us w o rd are s a v ed i n t he s t ack area. at t he s a m e ti m e , t he con t en t s o f t h e v e c t o r addre s s corre s pond i ng t o t he accep t e d i n t e rrupt, w h i c h i s i n t he i n t e rrupt v e c t or t ab l e , en t er s i n t o t h e program coun t e r and i n t e rrupt s e r v ice rout i n e i s e x ec u t ed. i n t h e i n t e rrupt s e r v i ce ro u t i ne, t he co r re s pond i ng i n t e rrupt reque s t f l a g i s c l eared an d i n t e rrupt m a s t er enab l e f l ag ( i - f l ag) bec o m e s " 0 " , t hereby ano t her i n t e rrup t s are not accep t ed b e f o r e i - f la g i s s e t t o " 1 " b y progr a m . i n order t o e x ecu t e t h e i n t e rrupt s e r v i c e rout i ne, i t i s neces s a ry t o w r i t e t h e j u m p addre s s ( t he f i r s t addres s of t h e i n t e r rupt s e r v i c e rout i ne) i n v e c t o r t a b l e corre s pond i ng t o eac h i n t e rrupt. i n terru p t a cce p t t i mi n g t h e v al i d tim i ng a f t e r e x ecut i ng i n t errupt control f l ag i - fl ag i s v a li d , a ft e r e i , d i e x e c u t e d ie n h , ie n l re g i s t er i s v a l i d a ft er n e x t i n s t ruct i on 1 c y c l e s 0 12 c y c l e s 8 c y c l e s s y s t e m cl o c k i n s t r u cti o n f e t c h in t e r r u pt o ve r h ead : 9 21 c y c l es int. r e q u e s t s a m p l i n g in t e r r u pt p r o c e s s s t ep i n t e rr u p t r o u t i n e a c o mm a n d b e f o r e i n t e rr u p t
GMS81508/16 41 interrupt process step timing 2.12.5. software interrupt the interrupt is the lowest priority order software interrupt by brk instruction. b-flag is set. interrupt vector of brk instruction is shared with the vector of tcall 0. each processing step is determined by b-flag as a below. execution of brk/ tcall0 0 brk or tcall0 1 tcall 0 routine brk interrupt routine ret b-flag ? reti v.l system clock instruction fetch sp-2 new pc v.h v.l sp-1 pc sp address bus psw opcode adh adl pcl v.l, v.h is vector address, adl, adh is start address of interrupt service routine as vector contents interrupt process step interrupt service routine not used pch data bus internal read internal write
hyundai microelectronics 42 2.12.6 . m u l ti p l e int e rr u pt w he n an i n t e rrupt i s accep t ed, and progr a m f l o w goe s t o t he i n t e rru p t s e r v i c e rou t i n e . t h e i n t e rrupt m a s t er enab l e f l ag ( i - f l ag) i s au t o m at i c a l ly c l eared and o t her i n t e rrup t s ar e i nh i b i t e d . w hen i n t e rrupt s e r v i c e i s c o m p l e t ed by r eti i n s t ruct i on, i - f l a g i s s e t au t o m a t i c a l l y. if o t he r i n t e rrup t s are genera t ed dur i ng i n t e rrupt s e r v i c e , t h e i n t e rrupt h a v ing h i gher pr i o r i t y i s accep t ed w hen t he pr e v i ou s i n t e rrupt s e r vi c e r o u ti n e i s c o m p l e t ed . i n order t o m u lt i p l e i n t e r rup t s , i - f l a g mu s t be c l eared by e i i n s t ruc t i o n w i t h i n t h e i n t e rrupt rout i ne. t hen, t h e h i gher p r i o r i t y i n t e rrupt i s accep t ed a m ong t h e i n t e rrup t s t hat i n t e rrupt reque s t f l ag i s " 1 " . i n t errupt mode reg i s t er ( i m o d ) if i m 1 ,i m 0 i s s e l e c t ed a s a " 01 " , t h e i n t e rrupt s e l e c t ed b y i p 0 ~ i p 3 can be accep t ed and o t her i n t e rrup t s are not accep t ed. u s i n g t h i s reg i s t er, w e can change t he i n t e rrupt p r i o r i t y order by s / w . i n t e rr u p t m o d e d e fi n i ti o n 00 : m o d e 0 ( p r i o r i t y b y h / w ) 0 1 : m o d e 1 ( d e f i n i t i o n b y i p 3 ip0) 1- : i n h i bit i n t e r r u p t in t err u pt d e f i n it i on s e l e c t i on 0 0 0 1 : i n t 0 0 0 1 0 : i n t 1 0 0 1 1 : i n t 2 0 1 0 0 : i n t 3 0 1 0 1 : t i m e r 0 0 1 1 0 : t i m e r 1 0 1 1 1 : t i m e r 2 1 0 0 0 : t i m e r 3 1 0 0 1 : a d c 1 0 10 : w d t 1 0 1 1 : b it 1 1 0 0 : s io < 00 f 3 h > i m od 7 6 5 i m 1 4 i m 0 3 ip3 2 ip2 1 ip1 0 ip0 r / w r / w r / w r / w r / w r / w
GMS81508/16 43 when multiple interrupt is accepted, it is possible to change interrupt accept mode. in case of multiple interrupt at hardware priority accept mode(mode0) in case of multiple interrupts nest h/w priority accept mode (mode0) and s/w selection accept mode(mode1) ei ei ei main program ( mode 0 ) 1st int. routine ( mode 0 ) 2nd int. routine ( mode 0 ) 3rd int. routine interrupt interrupt interrupt ei ei ei main program ( mode 0 ) 1st int. routine ( mode 0 ) 2nd int. routine ( mode 1 ) 3rd int. routine interrupt interrupt interrupt reload imod stacking imod change mode
hyundai microelectronics 44 2.13. s t a ndb y f unc t i on t o s a v e t he con s um i ng po w er of d e v ice, GMS81508 / 16 ha s s t o p mode. i n t h i s m ode, t he e x ec u t i o n o f progr a m i s s t opped. s t o p mode en t ered by s t op i n s t ruct i on. at s t op mode, d e v ice o perat i on s t a t e. p e r iph e r a l f un c t i o n s t o p m ode o s c i l l a t or
cpu c l ock
ram, re g i s t er re t a i n i/ o p o rt r e t a in pre s ca l er
b a s ic i n t e r v a l t i m e r
ser i a l i / o o pera t i on ( e x t e rn a l c l oc k se l e c t i on) w d t, t i m e r, a / dc , p w m , buzzer d r i v er
addres s bu s , da t a bus re t a i n rd, w t, r / w re t a i n halt, br q , b a k ac t i v e c " l " l e v e l sync "h" l e v e l ha l t s t o p if b it cpu c l ock re l ea s e s i gnal f r o m i n t errupt c i r cuit reset c l ock p u l s e ge n . mux pre s ca l er rq sq o v e r f l ow detect i on b a s ic i n t e r v a l t i m e r rq sq os c . c i rc u i t
GMS81508/16 45 2.13.1. stop mode stop mode can be entered by stop instruction during program execution. in stop mode, oscillator is st opped to make all clocks stop, which leads to the mode requiring much less power consumption. all register and ram data are preserved. caution) nop instruction have to be written more than 2 to next lines of stop instruction. 2.13.2. stop mode release the release of stop mode is done by reset input or interrupt. when there is a release signal of stop mode, the instruction execution is started after stabilization oscillation time set by program. after releasing stop mode, instruction execution is different by i-flag(bit 2 of psw). if i-flag = 1 entered interrupt service routine, if i-flag = 0 execute program from next instruction of stop instruction. stop mode release release factor release method reset by reset pin=low level, and device is initialized. int0,int1 int2,int3 in the state of enable flag=1 corresponding to each interrupt at the edge. serial i/o when serial i/o is executed by external clock, stop mode is released. release timing of stop mode system clock release signal by interrupt stop stabilization oscillation time stop mode determined by program. reset stabilization oscillation time + 8 cycles
hyundai microelectronics 46 w he n re l ea s e t he s t op mode, t o s ecure o s c i l l at i on s t abil i zat i on ti m e , w e u s e ba s i c i n t e r v a l ti m e r. so, b e f ore e x ecut i o n st o p i n s t ruct i on, w e m u s t s e l ect s u i t a b l e b . i . t. c l ock f or o s cil l at i on s t ab i l i zat i on ti m e . ot her w i s e , i t i s po s s i b l e t o r e l ea s e by on l y r es e t i npu t . becau s e s t o p m od e i s r e l ea s ed by i n t e rrupt, e v e n if bo t h o f i n t e rrupt enab l e bi t ( i e ) an d i n t e rrupt reque s t f l a g i s " 1 " , s t o p m od e can not be e x ec u t ed. s t op m o d e re l eas i ng f l o w 0 1 n o p n o p i n t errupt se r v ice rout i ne i -f l ag ? 0 1 s t op mode r e l ea s e i n t errupt reque s t ie ? s t op mode s t op c o m m an d
GMS81508/16 47 2.14. reset function to reset the device, maintain the reset="l" at least 8 machine cycle after power supplying and oscillation stabilization. reset terminal is organized as schmitt input. if initial value is undefined, it is needed initialize by a s/w. reset operation timing opcode system clock instruction fetch ? start ffff fffe ? ? ? address bus fe ? adh adl ? fffe h , is vector address and adl, adh is start address of main program as vector contents reset process step main program ? ? data bus internal read reset
hyundai microelectronics 48 3 . i/o po r ts t here are 7-por t s (r0 ~ r6) i n t h i s d e v i c e . t h i s por t s are doub l e- f un c t i on a l por t s and t h e f unct i on can be s e l e c t ed by progr a m . t he d i re c t i on o f po r t s i s de t e r m i ned by po r t d i rect i on reg i s t er . ( 1 = ou t put, 0 = i npu t ) t he da t a t hat i s w r i tt en on t he progr a m m e d ou t put p i n i s s t ored i n t he port da t a reg i s t er an d i s t ran s f e rre d t o t h e ou t put p i n. w hen d a t a i s i nput t o t he progr a mmed p i n . da t a i s read not f r o m ou t p u t p i n but f r o m po r t da t a reg i s t er. t her e f ore, pr e v iou s l y ou t p u t da t a ca n be read correct l y regard l e s s or t he l o g i c a l l e v e l of t he p i n due t o ou t put l oad i ng. becau s e t he program m e d i nput p i n i s f l oa t i n g , t h e v a l ue o f t h e p i n can be read correct l y . w hen da t a i s w r i tt e n t o t he progr a m m e d i nput p i n, i t i s w r i tt en only t o t he port da t a re g i s t er and t he p i n re m a i n s f l o a t i ng. 3.1. r0 port r0 port i s c o m po s ed of 8- b i t progr a m m ab l e i / o p i n. re g i ster name sym b ol r / w a d d ress i n it i al val u e r0 i /o d i rect i on reg i s t er r0dd w 00c1 h 0000 0000 r0 p o rt da t a re g i s t er r0 r/w 00c0 h n o t i n i t i a l i z e d r0 p o r t i / o d i re c t i o n r e gi s t er r0 p o r t d a t a reg i s t er d e t e r m i n e s i/o o f r 0 p o r t 0 : i n put 1 : o u t put < 00c1 h > r0dd 7 r0dd7 6 r0dd6 5 r0dd5 4 r0dd4 3 r0dd3 2 r0dd2 1 r0dd1 0 r0dd0 w w w w w w w w p o r t r 0 o u t p ut d a t a < 00c0 h > r0 7 r 0 7 6 r 0 6 5 r 0 5 4 r 0 4 3 r 0 3 2 r 0 2 1 r 0 1 0 r 0 0 r / w r / w r / w r / w r / w r / w r / w r / w
GMS81508/16 49 pin function according to operation modes pin single chip mode microprocessor mode r00/d0 i/o i/o r01/d1 i/o i/o r02/d2 i/o programmable i/o port i/o data i/o port from/to external memory r03/d3 i/o i/o for cpu. r04/d4 i/o i/o r05/d5 i/o i/o r06/d6 i/o i/o r07/d7 i/o i/o 3.2. r1 port r1 port is composed of 8-bit programmable i/o pin. register name symbol r/w address initial value r0 i/o direction register r1dd w 00c3 h 0000 0000 r0 port data register r1 r/w 00c2 h not initialized r1 port i/o direction register r1 port data register pin function according to operation modes determines i/o of r1 port 0 : input 1 : output <00c3 h > r1dd 7 r1dd7 6 r1dd6 5 r1dd5 4 r1dd4 3 r1dd3 2 r1dd2 1 r1dd1 0 r1dd0 w w w w w w w w port r1 output data <00c2 h > r1 7 r17 6 r16 5 r15 4 r14 3 r13 2 r12 1 r1 0 r10 r/w r/w r/w r/w r/w r/w r/w r/w
hyundai microelectronics 50 p i n s i ng l e ch i p mode m i croproce s s o r mode r 10 / a 0 i/o o r 11 / a 1 i/o o r 12 / a 2 i/o p r o g r a mm a b l e i/o p o r t o l o w 8 b it a d d r e s s o f e x t e r n al m e m o r y r 1 3 / a3 i / o o f o r c p u. r 14 / a 4 i/o o r 15 / a 5 i/o o r 16 / a 6 i/o o r 17 / a 7 i/o o 3.3. r2 port r2 port i s c o m po s ed of 8- b i t progr a m m ab l e i / o p i n. re g i ster name sym b ol r / w a d d ress i n it i al val u e r2 i /o d i rect i on reg i s t er r2dd w 00c5 h 0000 0000 r2 p o rt da t a re g i s t er r2 r/w 00c4 h n o t i n i t i a l i z e d r2 p o r t i / o d i re c t i o n r e gi s t er r2 p o r t d a t a reg i s t er d e t e r m i n e s i/o o f r 2 p o r t 0 : i n put 1 : o u t put < 00c5 h > r2dd 7 r2dd7 6 r2dd6 5 r2dd5 4 r2dd4 3 r2dd3 2 r2dd2 1 r2dd1 0 r2dd0 w w w w w w w w p o r t r 2 o u t p ut d a t a < 00c4 h > r2 7 r 2 7 6 r 2 6 5 r 2 5 4 r 2 4 3 r 2 3 2 r 2 2 1 r 2 1 0 r 2 0 r / w r / w r / w r / w r / w r / w r / w r / w
GMS81508/16 51 pin function according to operation modes pin single chip mode microprocessor mode r20/a8 i/o o r21/a9 i/o o r22/a10 i/o programmable i/o port o upper 8bit address of external memory r23/a11 i/o o for cpu. r24/a12 i/o o r25/a13 i/o o r26/a14 i/o o r27/a15 i/o o 3.4. r3 port r3 port is composed of 8-bit programmable i/o pin. register name symbol r/w address initial value r3 i/o direction register r3dd w 00c7 h 0000 0000 r3 port data register r3 r/w 00c6 h not initialized r3 port i/o direction register r3 port data register determines i/o of r3 port 0 : input 1 : output <00c7 h > r3dd 7 r3dd7 6 r3dd6 5 r3dd5 4 r3dd4 3 r3dd3 2 r3dd2 1 r3dd1 0 r3dd0 w w w w w w w w port r3 output data <00c6 h > r3 7 r37 6 r36 5 r35 4 r34 3 r33 2 r32 1 r31 0 r30 r/w r/w r/w r/w r/w r/w r/w r/w
hyundai microelectronics 52 p i n f un ct i on a cc o r d i n g t o o p era t i on m o d es p i n s i ng l e ch i p mode m i croproce s s o r mode r 30 i/o o r d : e x t e r n a l m e m o r y r ead s t r o b e r 31 i/o o w t : ex t er n al m e m o r y w r i t e s t r o b e r 32 i/o p r o g r a m m a b l e i/o p o r t o r / w : r ead/ w r it e c y c l e o u t p ut p i n o f c p u r 33 i/o o c : t i m i n g s i g n a l o u t p ut p i n r34 i/o o sync : op c o d e f e t c h ou t put p in o f cpu r 3 5 i/o o b r k : bus a c k n o w l ed g e ou t p u t pin o f cpu r 36 i/o i b r q : bus r e q u e s t i n p u t p in o f c u p r 37 i/o i h alt : c pu h alt i n p u t p i n 3.5. r4 port r4 port i s c o m po s ed of 8 b i t progr a m m ab l e i /o po r t and t h i s port are dou b l e f un c t i on a l p i n. re g i ster name sym b ol r / w a d d r ess i n it i al val u e r4 i /o d i rect i on reg i s t er r4dd w 00c9 h 0000 0000 r4 port da t a reg i s t er r4 r/w 00c8 h n o t i n i t i a l i z e d port r4 mode re g i s t er pmr4 w 00d0 h 0000 0000 i n t errupt edg e se l e c t reg i s t er i eds r/w 00 f 8 h 0000 0000 r4 p o r t i / o d i re c t i o n r e gi s t er r4 p o r t d a t a reg i s t er p o r t r 4 o u t p ut d a t a < 00c8 h > r4 7 r 4 7 6 r 4 6 5 r 4 5 4 r 4 4 3 r 4 3 2 r 4 2 1 r 4 1 0 r 4 0 r / w r / w r / w r / w r / w r / w r / w r / w d e t e r m i n e s i/o o f r 4 p o r t 0 : i n put 1 : o u t put < 00c9 h > r4dd 7 r4dd7 6 r4dd6 5 r4dd5 4 r4dd4 3 r4dd3 2 r4dd2 1 r4dd1 0 r4dd0 w w w w w w w w
GMS81508/16 53 port r4 mode register interrupt edge selection register 3.6. r5 port r5 port is composed of 8-bit programmable i/o port. r54,r55 is double functional pin. register name symbol r/w address initial value r5 i/o direction register r5dd w 00cb h 0000 0000 r5 port data register r5 r/w 00ca h not initialized r5 port mode register pmr5 w 00d1 h --00 ---- <00d0 h > pmr4 7 t3s 6 t1s 5 ec2s 4 ec0s 3 int3s 2 int2s 1 int1s 0 int0s w w w w w w r45/ ec2 selection 0 : r45 ( input / output ) 1 : ec2 ( input ) r44/ ec0 selection 0 : r44 ( input / output ) 1 : ec0 ( input ) r47 / t3 selection 0 : r47 ( input / output ) 1 : t3 ( output ) r46 / t1 selection 0 : r46 ( input / output ) 1 : t1 ( output ) r40 / int0 selection 0 : r40 ( input / output ) 1 : int0 ( input ) r41 / int1 selection 0 : r41 ( input / output ) 1 : int1 ( input ) r42 / int2 selection 0 : r42 ( input / output ) 1 : int2 ( input ) r43 / int3 selection 0 : r43 ( input / output ) 1 : int3 ( input ) w w <00f8 h > ieds 7 ied3h 6 ied3l 5 ied2h 4 ied2l 3 ied1h 2 ied1l 1 ied0h 0 ied0l w w w w w w int0 edge selection 01 : falling 10 : rising 11 : falling & rising int1 edge selection 01 : falling 10 : rising 11 : falling & rising int2 edge selection 01 : falling 10 : rising 11 : falling & rising int3 edge selection 01 : falling 10 : rising 11 : falling & rising w w
hyundai microelectronics 54 r5 p o r t i / o d i re c t i o n r e gi s t er r5 p o r t d a t a reg i s t er p o r t r5 m o de r e g i s t er 3.7. r6 port r6 port con s i s t s of 4-bit p rogrammab l e i /o po r t s and 4-b i t i nput on l y por t s and t h i s port can be u s ed a s a ana l og i nput port f o r a / d co n v er s i on by progr a m . re g i ster name sym b ol r / w a d d r ess i n it i al val u e r6 i /o d i rect i on reg i s t er r6dd w 00cd h 0000 ---- r6 port da t a reg i s t er r6 r/w 00cc h n o t i n i t i a l i z e d a / d co n v er t e r mode reg i s t er adcm w 00e8 h --00 000 1 p o rt r 5 o ut p ut d a t a < 00ca h > r5 7 r 5 7 6 r 5 6 5 r 5 5 4 r 5 4 3 r 5 3 2 r 5 2 1 r 5 1 0 r 5 0 r / w r / w r / w r / w r / w r / w r / w r / w d e t e r m i n e s i/o o f r 5 p o r t 0 : i n put 1 : o u t put < 00cb h > r5dd 7 r5dd7 6 r5dd6 5 r5dd5 4 r5dd4 3 r5dd3 2 r5dd2 1 r5dd1 0 r5dd0 w w w w w w w < 00d1 h > pmr5 7 - 6 - 5 buz 4 w d t o n 3 - 2 - 1 - 0 - w w r 55 / b u z s e l e cti o n 0 : r 55 ( i n p u t / o u t p ut ) 1 : buz ( o u t p u t ) r 5 4 / w d t o n s e l e c t i o n 0 : r 54 ( i n p u t / o u t p ut ) 1 : w d t o n ( o ut p ut ) w
GMS81508/16 55 r6 port i/o direction register r6 port data register on the initial reset, r60 cant be used digital input port, because this port is selected as an analog input port by adcm register. to use this port as a digital i/o port, change the value of lower 4 bits of adcm(address 0e8h). on the other hand,r6 port, all eight pins can not be used as digital i/o port simultaneously. at least one pin is used as an analog input. unused ports all unused ports should be set properly that current flow through port doesn't exist. first consider the setting the port as an input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed level voltage is applied to input pin, there can be little current ( max. 1ma at 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. port r6 output data <00cc h > r6 7 r47 6 r46 5 r45 4 r44 3 r43 2 r42 1 r41 0 r40 r/w r/w r/w r r r/w determines i/o of r6 port 0 : input 1 : output <00cd h > r6dd 7 r6dd7 6 r6dd6 5 r6dd5 4 r6dd4 3 r6dd3 2 r6dd2 1 r6dd1 0 r6dd0 w w w w r r
hyundai microelectronics 56 3.8. t erm i n a l t ypes p i n t erm i n a l t ype xin x o ut reset mp r00 ~ r07 rd data b us vss data b us 1 mux 0 mux d i r e c t i on r e g . vdd data b us data b us data r e g . mp rd data b us xin xout vdd vss s t o p vss
GMS81508/16 57 r10 ~ r27 r20 ~ r27 r30 r31 r32 r33 r34 r35 r36 r37 data bus data bus data bus vss mux mux vdd mp from r30 ... rd from r31 ... wt from r32 ... r/w from r33 ... c from r34 ... sync from r35 ... bak data reg. direction reg. rd data bus data bus data bus vss mux vdd mp data reg. direction reg. rd to brq to halt data bus data bus address bus data bus vss mux mux vdd mp data reg. direction reg. rd
hyundai microelectronics 58 r40/ i n t 0 r41/ i n t 1 r42/ i n t 2 r43/ i n t 3 r44/ e c0 r45/ e c2 r50/ s in r46 / t 1 o r47 / t 3 o r51/ s o u t r54/w d t o r55/buz r56/ p w m 0 r57/ p w m 1 r52/sclk t o r4 0 i n t 0 t o r4 1 i n t 1 t o r4 2 i n t 2 t o r4 3 i n t 3 t o r4 4 e c 0 t o r4 5 e c 2 t o r5 0 sin data b us vss data b us mux vdd s e l e c t i o n data b us data r e g . d i r e c t i on r e g . rd t o r4 0 i n t 0 t o r4 1 i n t 1 t o r4 2 i n t 2 t o r4 3 i n t 3 t o r4 4 e c 0 t o r4 5 e c 2 t o r5 0 sin data b us vss data b us mux vdd s e l e c t i o n data b us data r e g . d i r e c t i on r e g . rd data b us data b us data b us vss mux mux vdd s e l e c t i o n f r om r46 ... t 1o f r om r47 ... t 3o f r om r51 ... s out f r om r54 .. . w d t o f r om r55 ... b uz f r om r56 ... p w m0 f r om r57 ... p w m1 data r e g . d i r e c t i on r e g . rd s c k o s c k i data b us e x c k data b us data b us vss mux mux mux vdd s e l e c t i o n data r e g . d i r e c t i on r e g .
GMS81508/16 59 r53/srdy r60/an0 r61/an1 r62/an2 r63/an3 r64/an4 r65/an5 r66/an6 r67/an7 rd srdy o srdy in data bus data bus data bus vss mux mux vdd selection srdy data reg. direction reg. to a/d converter data bus vss data bus mux direction reg. vdd data bus data reg. rd data bus to a/d converter rd
hyundai microelectronics 60 4 . e l e c t r i c al c h a r a c t e r i s t i c s 4 . 1 . a b o u l u t e m a x im u m r a t i n g s p a r a m e t er s ym b ol u nit r a t i ngs su p p l y v o l t a g e vdd v - 0.3 ~ 7 . 0 in p u t v ol t a g e vi v -0.3 ~ v d d + 0.3 s t o r a g e t em p e r atu r e t s tg c - 40 ~ 1 2 5 4.2. recom m en d ed ope r a t i ng con d i t i ons p a r a m e t e r s y m b o l u n i t s p e c i f i c a ti o n s m i n. t yp. m ax. s u p p l y v o l t a g e v dd v 4 .5 5.5 o p e r at i ng f r e q u en c y f x in m h z 1 8 o p e r at i ng t e m p e r a t u r e t o p r c - 2 0 8 5 4.3. a /d con v er t er ch a r a c t eris t i cs ( v d d = 5v 1 0 % , v s s = 0 , , f ( x i n ) = 8 ) p a r a m e t e r p i n s y m b o l u n i t speci f ica t i o n e t c m i n. t yp. m ax. a n a l og i n p u t r a ng e a n 0 ~ a n 7 v a i n v v s s v r e f a cc u r a c y l s b 3 c o n ve r s i on t i m e t c o n v 20 a n a l o g p o w e r s up p i y i n p u t r a nge a v r e f v r e f v v d d
GMS81508/16 61 4.4. dc characteristics ( vdd =5.0v 10%,vss = 0 , ta = -20 85 ,f (xin) = 8 ) parameter symbol pin test condition unit specifications min. typ. max. reset,,r4,r5,r6 0.8vdd vdd "h" input voltage vih r0,r1,r2,r3 v 0.7vdd vdd xin 0.9vdd vdd reset,r4,r5,r6 0 0.12vdd "l" input voltage vil r0,r1,r2,r3 v 0 0.3vdd xin 0 0.1vdd "h" input leakage current iih all input pins vi = vdd -5 5 "l" input leakage current iil all input pins vi = vss -5 5 "h" output voltage voh r0,r1,r2,r3,r4,r5 ioh = -2ma v vdd-1 "l" output voltage r0,r1,r2,r3,r4,r5 iol = 5ma v 1.0 power operating idd all input = vss
20 40 current stop istop 20 100 hysteresis v t + ~ v t - reset, v 0.3 0.8 ec2,ec0,sin,sclk,int0~3 0.3 0.8 ram data retention vram vdd at clock stop v 2.0
hyundai microelectronics 62 4.5. a c c h a r ac t er i s t i cs 4.5.1. inpu t con d i t ions ( v d d = 5 . 0 v 1 0 % , v ss = 0 , t a = - 2 0 8 5 ,f (xin) = 8 ) p a r a m e t er pin s y m b ol unit speci f ica t i o n e t c mi n . t y p . m a x . o p e r at i ng f r e q u en c y xin f c p m h z 1 - 8 s y st e m c l o c k t s y s n s 5 00 - 2 50 o sc il l a t i on s t a b i l i z a t i on t i m e xin, xout t st ms 20 e x t e r n al c l o c k p ul s e w idth x in t c p w ns 1 0 0 e x t e r n al c l o c k t r an s it i on t i m e x in t r c p,t f c p ns 20 in t e rr u pt p u l s e w idth i n t 0~i n t 3 t iw t s y s 2 reset i n put " l" w idth reset t r s t t s y s 8 e vent c oun t er i n put p u l s e w idth e c 0, e c 2 t e c w t s y s 2 e vent c oun t er t r an s i t i on t i m e e c 0, e c 2 t r e c , t f ec ns 20 ti m i n g c h a r t reset x i n t fcp t r c p 0.5 v v dd - 0 . 5v t c p w 1/f cp t c p w int3 int2 int1 int0 0.2 v d d 0.8 v d d t iw t iw t rst 0.2 v d d ec0 ec2 0.2 v d d 0.8 v d d 0.8 v d d t e c w t e c w t rec t f e c
GMS81508/16 63 4.5.2. serial transfer ( vdd = 5.0v 10%, vss = 0 , ta = -20 85 ,f (xin) = 8 ) parametet pin symbol unit specification etc min. typ. max. serial input clock pulse sclk tscyc ns 2tsys+200 - 8 serial input clock pulse width sclk tsckw ns tsys+70 - 8 serial input clock pulse transition time sclk tfsck,trsck ns - 30 sin input pulse transition time sin tfsin,trsin ns - 30 sin input setup time(exnternal sclk) sin tsus ns 100 - sin input setup time(internal sclk) sin tsus ns 200 - sin input hold time sin ths ns tsys+70 - serial output clock cycle time sclk tscyc ns 4tsys - 16tsys serial output clock transition time sclk tsckw ns 2tsys-30 - serial output clock transition time sclk tfsck,trsck ns - 30 serial output delay time sout tr ec, tf ec ns 100 serial i/o timing chart sin sclk 0.2 vdd sout 0.2 vdd 0.8 vdd t hs t sus t fsin t rsin 0.2 vdd 0.8 vdd t ds t fsck 0.8 vdd t scyc t sckw t sckw t rsck
hyundai microelectronics 64 4.5.3 . m i crop r ocessor m od e i/o t i m i ng ( v d d = 5 . 0 v 1 0 % , v ss = 0 , t a = - 2 0 8 5 ,f (xin) = 8 ) p a r a m e t er pin s y m b ol unit speci f ica t i o n etc mi n . t y p . m a x . c o nt r ol c l o c k o u t put w idth c t c l ns 90 - a dd r e s s o u t p u t d e l ay t i m e a 0 ~ a 15 td c a ns - 80 d a t a o u t p u t d e l a y t i me d 0 ~ d7 t d cd n s - 1 8 0 d a t a o u t p u t h old t i m e d 0 ~ d 7 t h w ns - 20 d a t a i np u t s e t up t i m e d 0 ~ d 7 t s ur ns 80 - d a t a i n p ut h o l d t i m e d 0 ~ d 7 thr ns 15 - r d o u t p ut d e l ay t i m e r d td r d t s y s - 90 w t o utput d e l ay t i m e w t t d w t t s y s - 1 3 0 r / w o utput d e l a y t i m e r / w td r w t s y s - 50 s ync o u t p ut d e l ay t i m e s y n c td s ync t s y s - 50 ti m i n g c h a r t t s ys t c w t c w 0. 8 v dd 0. 8 v dd 0. 2 v d d 0. 2 v dd t d ca t d cd t s tr t d rd t d wt t d rw 0. 8 v dd 0. 2 v dd td s y n c 0. 8 v dd 0. 2 v dd thr thw 0. 2 v dd 0. 2 v dd 0. 8 v dd 0. 2 v dd c a 0 ~ a 15 w ri t e m ode d 0 ~ d 7 r e a d m o d e d 0 ~ d 7 rd wt r/w s ync
GMS81508/16 65 4.5.4. bus holding timing ( vdd = 5.0v 10%, vss = 0 , ta = -20 85 ,f (xin) = 8 ) parameter pin symbol unit specification etc min. typ. max. brq setup time brq tsub tsys 100 - bak delay time bak tdba tsys - 50 bak release delay time bak tdrba tsys - 220 bus(address,data) control release delay time d0 ~ d7 a0 ~ a15 rd,w t,r/w tdra tsys - 210 timing chart instruction ececution holding cycle instruction ececution 0.2vdd 0.2vdd 0.2vdd 0.2vdd 0.8vdd 0.8vdd 0.2vdd tdba tsub tsub tdrba tdra hi-z c sync brq baq d0~d7 a0~a15 rd wt r/w
hyundai microelectronics 66 5. ins t ru c t i o n set 1. arith m etic/ logic operation no. m n e m o n i c op co d e b y t e no c y c l e no o p e r a t i o n f l a g nvgbhizc 1 ad c # i m m 0 4 2 2 a d d w i t h c a r r y . 2 ad c d p 0 5 2 3 a ( a )
( m )
c
g m s 81508/16 67 no. m n e m o n i c op co d e b y t e no c y c l e no o p e r a t i o n f l a g nvgbhizc 3 8 de c a a8 1 2 d e cc r e m e n t n-----z - 3 9 de c d p a9 2 4 m ( m ) 1 n-----z-
68 no. m n e m o n i c op co d e b y t e no c y c l e no o p e r a t i o n f l a g nvgbhizc 80 s b c # i mm 24 2 2 s ub s t r a c t w ith c a r r y 81 s b c d p 25 2 3 a ( a ) ( m ) ( c )
GMS81508/16 69 no. mnemonic code no no operation nvgbhizc 27 stx dp ec 2 4 store x-register contents in memoy 28 stx dp + y ed 2 5 ( m ) x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memoy 31 sty dp + x f9 2 5 ( m ) y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x y -------- 3. 16-bit operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ( ya )
( dp +1 ) ( dp ) nv--h-zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) (dp+1)(dp) n-----zc 3 decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ( dp+1) ( dp )
1 n-----z- 5 ldya dp 7d 2 5 load ya ya ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ya -------- 7 subw dp 3d 2 5 16-bits substact without carry ya ( ya ) ( dp +1) ( dp) nv--h-zc
hyundai microelectronics 70 4. bit manipula t ion no. m n e m o n i c op co d e b y t e no c y c l e no o p e r a t i o n f l a g nvgbhizc 1 and 1 m . b i t 8 b 3 4 bit a n d c- f l ag : c ( c ) ( m . b i t ) -------c 2 and 1 b m . b i t 8 b 3 4 b it a n d c - f l a g a n d n o t : c ( c ) ( m . b i t ) -------c 3 bit dp 0c 2 4 bit t e s t a w i t h m e m o r y : mm----z- 4 b it ! abs 1c 3 5 z ( a ) ( m ) , n ( m 7 ) , v ( m 6 )
GMS81508/16 71 no. mnemonic op code byte no cycle no operation flag nvgbhizc 8 bmi rel 90 2 2/4 branch if minus if ( n ) 1 , then pc ( pc )
rel -------- 9bne rel 70 2 2/4 branch if not equal if ( z ) 0 , then -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) 0 , then pc ( pc )
rel -------- 11 bra rel 2f 2 4 branch always pc ( pc )
rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) 0 , then pc ( pc)
rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) 1 , then pc ( pc )
rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ( pc h ), sp sp - 1, m( sp) ( pc l ), sp sp - 1, if !abs, pc abs ; if [dp], pc l ( dp ), pc h ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) ( m ) , then pc ( pc )
rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 0 , then pc ( pc )
rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m( sp) ( pc h ), sp sp - 1, m( sp) ( pc l ), sp sp - 1, pc l ( upage ), pc h 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ( pc h ), sp sp - 1, m( sp) ( pc l ),sp sp - 1, pc l (table vector l), pc h (table vector h) --------
hyundai microelectronics 72 6. con t rol opera t ion & etc. no. m n e m o n i c op co d e b y t e no c y c l e no o p e r a t i o n f l a g nvgbhizc 1 b r k 0 f 1 8 s o f t w a r e i n t e r r u p t : b 1 , m ( s p ) ( p c h ), s p s p - 1 , m ( s ) ( p c l ), s p s p - 1 , m ( s p ) ( p s w ), s p s p - 1 , pc l ( 0 f fde h ) , pc h ( 0ff d f h ) . ---1-0-- 2 d i 6 0 1 3 d i s a b l e i n t e r r ups : i 0 -----0-- 3 e i e 0 1 3 e n ab l e i n t e r r u ps : i 1 -----1-- 4 n o p ff 1 2 n o o p e r a t i on -------- 5 p o p a 0 d 1 4 s p s p
1, a m( s p ) 6 p o p x 2 d 1 4 s p s p
1 , x m( s p ) --------
6 . gms81516at (otp) programming the gms81516at is one-time prom (otp) micro - controller with 16k bytes electrically programmable read only memory for the GMS81508/16 system evaluation, first production and fast mass production. to programming the otp device, user can have two way. one is using the universal programmer which is support hme microcontrollers, other is using the gen - eral eprom programmer. 1. using the universal programmer third party universal programmer support to program the gms81516at microcontrollers and lists are shown as below. manufacturer: advantech web site: http://www.aec.com.tw programmer: labtool-48 manufacturer: hi-lo systems web site: http://www.hilosystems.com.tw programmer: all-11, gang-08 socket adapters are supported by third party program - mer manufacturer. 2. using the general eprom(27c256) programmer the programming algorithm is simmilar with the stan - dart eprom 27c256. it give s some convience that user can use standard eprom programmer. make sure that 1ms programming pulse must be used, it gener - ally called "intelligent mode". do not use 100us programming pulse mode, "quick pulse mode". when user use general eprom programmer, socket adaper is essencially required. it convert pin to fit the pin of general 27c256 eprom. three type socket adapters are provided according to package variation as below table. socket adapter package type oa815a-64sd 64 pin sdip oa815a-64qf-10 64 pin l qfp (10 x 10) oa815a-64qf 64 pin qfp (14 x 20) with these socket adapters, the gms81516at can easy be programming and verifying using intel 27c256 eprom mode on general-purpose prom programmer. in assembler and file type, two files are generated after compiling. one is "*.hex", another is "*.otp". the "*.hex" file is used for emulation in circuit emulator (choice-dr tm or choice-jr tm ) and "*.otp" file is used for programming to the otp device. programming procedure 1. select the eprom device and manufacturer on eprom programmer (intel 27c256). 2. select the programming algorithm as an intelligent mode (apply 1ms writing pulse), not a quick pulse mode. 3. load the file (*.otp) to the programmer. 4. set the programming address range as below table. address set value buffer start address 4000 h buffer end address 7fff h device start address 4000 h 5. mount the socket adapter with the gms815 16at on the prom programmer. 6. start the prom programmer to programming/ verifying. gms81 5 08 /1 6 hyundai microelectronics
gms81516 a t programm ing manual
device overview the gms81516at is a high-performance cmos 8-bit microcontroller with 16k bytes of eprom. the d evice is one of gms800 family. the hme gms81516at is a powerful microcontroller which prov ides a highly flexible and cost effective solution to many embedded control applications. the gms81516a t provides the following standard features: 16k bytes of eprom, 448 bytes of ram, 56 i/o lines, 16-bit or 8-bit timer/counter, a precision analog to digital converter, pwm, on-chip oscillator and clock circuitry. pin configuration 64sdip gms81516at hyundai microelectronics gms81516at eprom programming 2
64lqfp 64qfp gms81516at eprom programming hyundai microelectronics 3
notes: (1) these pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) these pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 1 v dd - v dd - 2 mp i v pp - 3 avss i (1) i 4 avref i (1) i 5 r67/an7 i/o (1) i 6 r66/an6 i/o (1) i 7 r65/an5 i/o (1) i 8 r64/an4 i/o (1) i 9 r63/an3 i (1) i 10 r62/an2 i (1) i 11 r61/an1 i (1) i 12 r60/an0 i (1) i 13 r57/pwm1 i/o (1) i 14 r56/pwm0 i/o (1) i 15 r55/buz i/o (1) i 16 r54/wdto i/o (1) i 17 r53/ srdy i/o (1) i 18 r52/sclk i/o (1) i 19 r51/sout i/o (1) i 20 r50/sin i/o (1) i 21 r47/t3o i/o (2) i 22 r46/t1o i/o (2) i 23 r45/ ec2 i/o ce i 24 r44/ ec0 i/o oe i 25 r43/int3 i/o (1) i 26 r42/int2 i/o (1) i 27 r41/int1 i/o (1) i 28 r40/int0 i/o (1) i 29 reset i (1) i 30 x in i (1) i 31 x out o (3) o 32 v ss - v ss - pin no. mcu mode otp mode 33 r27 i/o a15 i 34 r26 i/o a14 i 35 r25 i/o a13 i 36 r24 i/o a12 i 37 r23 i/o a11 i 38 r22 i/o a10 i 39 r21 i/o a9 i 40 r20 i/o a8 i 41 r17 i/o a7 i 42 r16 i/o a6 i 43 r15 i/o a5 i 44 r14 i/o a4 i 45 r13 i/o a3 i 46 r12 i/o a2 i 47 r11 i/o a1 i 48 r10 i/o a0 i 49 r07 i/o o7 i/o 50 r06 i/o o6 i/o 51 r05 i/o o5 i/o 52 r04 i/o o4 i/o 53 r03 i/o o3 i/o 54 r02 i/o o2 i/o 55 r01 i/o o1 i/o 56 r00 i/o o0 i/o 57 r37 i/o (1) i 58 r36 i/o (1) i 59 r35 i/o (1) i 60 r34 i/o (1) i 61 r33 i/o (1) i 62 r32 i/o (1) i 63 r31 i/o (1) i 64 r30 i/o (1) i i/o: input/output pin i: input pin o: output pin 64sdip package for gms81516at hyundai microelectronics gms81516at eprom programming 4
notes: (1) these pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) these pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 1 r65/an5 i/o (1) i 2 r64/an4 i/o (1) i 3 r63/an3 i (1) i 4 r62/an2 i (1) i 5 r61/an1 i (1) i 6 r60/an0 i (1) i 7 r57/pwm1 i/o (1) i 8 r56/pwm0 i/o (1) i 9 r55/buz i/o (1) i 10 r54/wdto i/o (1) i 11 r53/ srdy i/o (1) i 12 r52/sclk i/o (1) i 13 r51/sout i/o (1) i 14 r50/sin i/o (1) i 15 r47/t3o i/o (2) i 16 r46/t1o i/o (2) i 17 r45/ ec2 i/o ce i 18 r44/ ec0 i/o oe i 19 r43/int3 i/o (1) i 20 r42/int2 i/o (1) i 21 r41/int1 i/o (1) i 22 r40/int0 i/o (1) i 23 reset i (1) i 24 x in i (1) i 25 x out o (3) o 26 v ss - v ss - 27 r27 i/o a15 i 28 r26 i/o a14 i 29 r25 i/o a13 i 30 r24 i/o a12 i 31 r23 i/o a11 i 32 r22 i/o a10 i pin no. mcu mode otp mode 33 r21 i/o a9 i 34 r20 i/o a8 i 35 r17 i/o a7 i 36 r16 i/o a6 i 37 r15 i/o a5 i 38 r14 i/o a4 i 39 r13 i/o a3 i 40 r12 i/o a2 i 41 r11 i/o a1 i 42 r10 i/o a0 i 43 r07 i/o o7 i/o 44 r06 i/o o6 i/o 45 r05 i/o o5 i/o 46 r04 i/o o4 i/o 47 r03 i/o o3 i/o 48 r02 i/o o2 i/o 49 r01 i/o o1 i/o 50 r00 i/o o0 i/o 51 r37 i/o (1) i 52 r36 i/o (1) i 53 r35 i/o (1) i 54 r34 i/o (1) i 55 r33 i/o (1) i 56 r32 i/o (1) i 57 r31 i/o (1) i 58 r30 i/o (1) i 59 v dd - v dd - 60 mp i v pp - 61 av ss i (1) i 62 av ref i (1) i 63 r67/an7 i/o (1) i 64 r66/an6 i/o (1) i i/o: input/output pin i: input pin o: output pin 64qfp package for gms81516at gms81516at eprom programming hyundai microelectronics 5
notes: (1) these pins must be connected to v ss , because these pins are input ports during programming, program verify and reading (2) these pins must be connected to v dd . (3) x out pin must be opened during programming. pin no. mcu mode otp mode 1 r63/an3 i (1) i 2 r62/an2 i (1) i 3 r61/an1 i (1) i 4 r60/an0 i (1) i 5 r57/pwm1 i/o (1) i 6 r56/pwm0 i/o (1) i 7 r55/buz i/o (1) i 8 r54/wdto i/o (1) i 9 r53/ srdy i/o (1) i 10 r52/sclk i/o (1) i 11 r51/sout i/o (1) i 12 r50/sin i/o (1) i 13 r47/t3o i/o (2) i 14 r46/t1o i/o (2) i 15 r45/ ec2 i/o ce i 16 r44/ ec0 i/o oe i 17 r43/int3 i/o (1) i 18 r42/int2 i/o (1) i 19 r41/int1 i/o (1) i 20 r40/int0 i/o (1) i 21 reset i (1) i 22 x in i (1) i 23 x out o (3) o 24 v ss - v ss - 25 r27 i/o a15 i 26 r26 i/o a14 i 27 r25 i/o a13 i 29 r24 i/o a12 i 29 r23 i/o a11 i 30 r22 i/o a10 i 31 r21 i/o a9 i 32 r20 i/o a8 i pin no. mcu mode otp mode 33 r17 i/o a7 i 34 r16 i/o a6 i 35 r15 i/o a5 i 36 r14 i/o a4 i 37 r13 i/o a3 i 38 r12 i/o a2 i 39 r11 i/o a1 i 40 r10 i/o a0 i 41 r07 i/o o7 i/o 42 r06 i/o o6 i/o 43 r05 i/o o5 i/o 44 r04 i/o o4 i/o 45 r03 i/o o3 i/o 46 r02 i/o o2 i/o 47 r01 i/o o1 i/o 48 r00 i/o o0 i/o 49 r37 i/o (1) i 50 r36 i/o (1) i 51 r35 i/o (1) i 52 r34 i/o (1) i 53 r33 i/o (1) i 54 r32 i/o (1) i 55 r31 i/o (1) i 56 r30 i/o (1) i 57 v dd - v dd - 58 mp i v pp - 59 av ss i (1) i 60 av ref i (1) i 61 r67/an7 i/o (1) i 62 r66/an6 i/o (1) i 63 r65/an5 i/o (1) i 64 r64/an4 i/o (1) i i/o: input/output pin i: input pin o: output pin 64lqfp package for gms81516at hyundai microelectronics gms81516at eprom programming 6
pin function (otp mode) v pp (program voltage) v pp is the input for the program voltage for programming the eprom. ce ( chip enable) ce is the input for programming and verifying internal eprom. oe (output enable) oe is the input of data output control signal for verify. a 0 ~a 15 (address bus) a 0 ~a 15 are address input pins for internal eprom. o 0 ~o 7 (eprom data bus) these are data bus for internal eprom. programming the gms81516at has address a 0 ~a 15 pins. therefore, the programmer just program the data (from 4000 h to 7fff h ) into the gms81516at otp device, during addresses a 14 ,a 15 must be pulled to a logic high. when the programmer write the data from 4000 h to 7fff h , consequently, the data actually will be written into addresses c000 h to ffff h of the otp device. 1. the data format to be programmed is made up of motorola s1 format. ex) "motorola s1" format; s0080000574154434880 s1244000e1ff3bff04a13f8f06e101711b821b1be01d1b3b191bf6181bf01c1bff081bff0ae0 s12440211bf5091bff0b1bff3f1b003e1b003d1b003c1bff3b1b003a1bff391bff381bff353d : : s1057ff2983fb2 s1057ffeff3f3f s9030000fc 2. down load above data into programmer from pc. 3. programming the data from address 4000 h to 7fff h into the otp mcu, the data must be turned over respectively, and then record the data. when read the data, it also must be turned over. ex) 00(00000000) ? ff(11111111), 76(01110110) ? 89(10001001), ff (11111111)? 00(00000000) etc. 4. of course, the check sum is result of the sum of whole data from address 4000 h to 7fff h in the file (not reverse data of otp mcu). * when gms81516at shipped, the blank data of gms81516at is initially 00 h (not ff h ). gms81516at eprom programming hyundai microelectronics 7
address gms81516at device file xxxxxxxx.otp e1 ff 3b ff 04 a1 3f 8f : : : : 98 3f : ff 3f down loadin g program 4000 h 4001 h 4002 h 4003 h 4004 h 4005 h 4006 h 4007 h : : : : 7ff2 h 7ff3 h : 7ffe h 7fff h e1 ff 3b ff 04 a1 3f 8f : : : : 98 3f : ff 3f 4000 h 4001 h 4002 h 4003 h 4004 h 4005 h 4006 h 4007 h : : : : 7ff2 h 7ff3 h : 7ffe h 7fff h 1e 00 c4 00 fc 5e c0 70 : : : : 67 c0 : 00 c0 c000 h c001 h c002 h c003 h c004 h c005 h c006 h c007 h : : : : fff2 h fff3 h : fffe h ffff h reading verify up loading data addres s data addres s data programmer buffer checksum = e1+ff+3b+ff+04+a1+3f+8f+ + 98+3f+ +ff+3f programming example program area 16 k bytes c000 h ffff h address file type: motorola s-format gms81516at 4000 h 7fff h address xxxxxxxx.otp universal programmer down loading program verify reading programming flow hyundai microelectronics gms81516at eprom programming 8
device operation mode (t a = 25 c 5 c) mode ce oe a 0 ~a 15 v pp v dd o 0 ~o 7 read x x v dd 5.0v d out output disable v ih v ih x v dd 5.0v hi-z programming v il v ih x v pp v dd d in program verify x x v pp v dd d out notes: 1. x = either v il or v ih 2. see dc characteristics table for v dd and v pp voltages during programming. dc characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition v pp intelligent programming 12.0 - 13.0 v v dd (1) intelligent programming 5.75 - 6.25 v i pp (2) v pp supply current 50 ma ce =v il i dd (2) v dd supply current 30 ma v ih input high voltage 0.8 v dd v v il input low voltage 0.2 v dd v v oh output high voltage v dd -1.0 v i oh = -2.5 ma v ol output low voltage 0.4 v i ol = 2.1 ma i il input leakage current 5 ua notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the maximum current value is with outputs o 0 to o 7 unloaded. gms81516at eprom programming hyundai microelectronics 9
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v 2. to read the output data, transition requires on the oe from the high to the low after address setup time t as . address valid t oe valid output t dh addresses oe output high-z v ih v il v ih v il v ih v il t as (2) reading waveforms waveform inputs outputs must be steady may change from h to l may change from l to h do not care any change permitted does not apply w ill be steady w ill be changing from h to l w ill be changing from l to h changing state unknown center line is high impedance "off" state switching waveforms hyundai microelectronics gms81516at eprom programming 10
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v t dfp addresses data high-z v ih v il 12.5v v dd v pp v dd ce oe 6.0v 5.0v t as t ds t vps t vds t opw t pw t oes program program verify t dh v ih v il v ih v il v ih v il t ah address stable data in stable data out valid t oe programming algorithm waveforms gms81516at eprom programming hyundai microelectronics 11
ac reading characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition t as address setup time 2 us t oe data output delay time 200 ns t dh data hold time 0 ns notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . ac programming characteristics (v ss =0 v, t a = 25 c 5 c; see dc characteristics table for v dd and v pp voltages.) symbol item min typ max unit condition* (note 1) t as address set-up time 2 us t oes oe set-up time 2 us t ds data setup time 2 us t ah address hold time 0 us t dh data hold time 1 us t dfp output disable delay time 0 us t vps v pp setup time 2 us t vds v dd setup time 2 us t pw program pulse width 0.95 1.0 1.05 ms intelligent t opw ce pulse width when over programming 2.85 78.75 ms (note 2) t oe data output delay time 200 ns *ac conditions of test input rise and fall times (10% to 90%) . . . . 20 ns input pulse levels . . . . . . . . . . . . . . . 0.45v to 4.55v input timing reference level . . . . . . . . . 1.0v to 4.0v output timing reference level . . . . . . . . 1.0v to 4.0v notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value x refer to page 13. hyundai microelectronics gms81516at eprom programming 12
start v dd = 6.0v v pp = 12.5v x = 0 program one 1 ms pulse increment x verify byte verify one byte last address ? v dd = v pp = 5.0v compare all bytes to original data device passed increment address yes no fail pass fail pass no yes fail pass device failed program one pulse of 3x msec duration x = 25 ? address= first location intelligent programming algorithm gms81516at eprom programming hyundai microelectronics 13

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